External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

2.2.1.3. Recommended Termination Schemes

The following table provides the recommended termination schemes for major DDR2 memory interface signals.

Signals include data (DQ), data strobe (DQS/DQSn), data mask (DM), clocks (mem_clk/mem_clk_n), and address and command signals.

When interfacing with multiple DDR2 SDRAM components where the address, command, and memory clock pins are connected to more than one load, follow these steps:

  1. Simulate the system to get the new slew-rate for these signals.
  2. Use the derated tIS and tIH specifications from the DDR2 SDRAM data sheet based on the simulation results.
  3. If timing deration causes your interface to fail timing requirements, consider signal duplication of these signals to lower their loading, and hence improve timing.
Note: Intel uses Class I and Class II termination in this table to refer to drive strength, and not physical termination.
Note: You must simulate your design for your system to ensure correct operation.
Table 27.  Termination Recommendations    (1)

Device Family

Signal Type

SSTL 18 IO Standard  (2) (3) (4) (5) (6)

FPGA-End Discrete Termination

Memory-End Termination 1 (Rank/DIMM)

Memory I/O Standard

Arria II GX

DDR2 component

DQ

Class I R50 CAL

50-ohm Parallel to VTT discrete

ODT75  (7)

HALF  (8)

DQS DIFF  (13)

DIFF Class R50 CAL

50-ohm Parallel to VTT discrete

ODT75  (7)

HALF  (8)

DQS SE  (12)

Class I R50 CAL

50-ohm Parallel to VTT discrete

ODT75  (7)

HALF  (8)

DM

Class I R50 CAL

N/A

ODT75  (7)

N/A

Address and command

Class I MAX

N/A

56-ohm parallel to VTT discrete

N/A

Clock

DIFF Class I R50 CAL

N/A

×1 = 100-ohm differential  (10)

×2 = 200-ohm differential  (11)

N/A

DDR2 DIMM

DQ

Class I R50 CAL

50-ohm Parallel to VTT discrete

ODT75  (7)

FULL  (9)

DQS DIFF  (13)

DIFF Class I R50 CAL

50-ohm Parallel to VTT discrete

ODT75  (7)

FULL  (9)

DQS SE  (12)

Class I R50 CAL

50-ohm Parallel to VTT discrete

ODT75  (7)

FULL  (9)

DM

Class I R50 CAL

N/A

ODT75  (7)

N/A

Address and command

Class I MAX

N/A

56-ohm parallel to VTT discrete

N/A

Clock

DIFF Class I R50 CAL

N/A

N/A = on DIMM

N/A

Arria V and Cyclone V

DDR2 component

DQ

Class I R50/P50 DYN CAL

N/A

ODT75  (7)

HALF  (8)

DQS DIFF  (13)

DIFF Class I R50/P50 DYN CAL

N/A

ODT75  (7)

HALF  (8)

DQS SE  (12)

Class I R50/P50 DYN CAL

N/A

ODT75  (7)

HALF  (8)

DM

Class I R50 CAL

N/A

ODT75  (7)

N/A

Address and command

Class I MAX

N/A

56-ohm parallel to VTT discrete

N/A

Clock

DIFF Class I R50 NO CAL

N/A

×1 = 100-ohm differential  (10)

×2 = 200-ohm differential  (11)

N/A

DDR2 DIMM

DQ

Class I R50/P50 DYN CAL

N/A

ODT75  (7)

FULL  (9)

DQS DIFF  (13)

DIFF Class I R50/P50 DYN CAL

N/A

ODT75  (7)

FULL  (9)

DQS SE  (12)

Class I R50/P50 DYN CAL

N/A

ODT75  (7)

FULL  (9)

DM

Class I R50 CAL

N/A

ODT75  (7)

N/A

Address and command

Class I MAX

N/A

56-ohm parallel to VTT discrete

N/A

Clock

DIFF Class I R50 NO CAL

N/A

N/A = on DIMM

N/A

Arria II GZ, Stratix III, Stratix IV, and Stratix V

DDR2 component

DQ

Class I R50/P50 DYN CAL

N/A

ODT75  (7)

HALF  (8)

DQS DIFF  (13)

DIFF Class I R50/P50 DYN CAL

N/A

ODT75  (7)

HALF  (8)

DQS SE  (12)

DIFF Class I R50/P50 DYN CAL

N/A

ODT75  (7)

HALF  (8)

DM

Class I R50 CAL

N/A

ODT75  (7)

N/A

Address and command

Class I MAX

N/A

56-ohm Parallel to VTT discrete

N/A

Clock

DIFF Class I R50 NO CAL

N/A

x1 = 100-ohm differential  (10)

x2 = 200-ohm differential  (11)

N/A

DDR2 DIMM

DQ

Class I R50/P50 DYN CAL

N/A

ODT75  (7)

FULL  (9)

DQS DIFF  (13)

DIFF Class I R50/P50 DYN CAL

N/A

ODT75  (7)

FULL  (9)

DQS SE  (12)

Class I R50/P50 DYN CAL

N/A

ODT75  (7)

FULL  (9)

DM

Class I R50 CAL

N/A

ODT75  (7)

N/A

Address and command

Class I MAX

N/A

56-ohm Parallel to VTT discrete

N/A

Clock

DIFF Class I R50 NO CAL

N/A

N/A = on DIMM

N/A

MAX 10

DDR2 component

DQ/DQS

Class I 12 mA

50-ohm Parallel to VTT discrete

ODT75  (7)

HALF  (8)

DM

Class I 12 mA

N/A

80-ohm Parallel to VTT discrete

N/A

Address and command

Class I MAX

N/A

N/A

Clock

Class I 12 mA

N/A

x1 = 100-ohm differential  (10)

x2 = 200-ohm differential  (11)

N/A

Notes to Table:

  1. N/A is not available.
  2. R is series resistor.
  3. P is parallel resistor.
  4. DYN is dynamic OCT.
  5. NO CAL is OCT without calibration.
  6. CAL is OCT with calibration.
  7. ODT75 vs. ODT50 on the memory has the effect of opening the eye more, with a limited increase in overshoot/undershoot.
  8. HALF is reduced drive strength.
  9. FULL is full drive strength.
  10. x1 is a single-device load.
  11. x2 is two-device load. For example, you can feed two out of nine devices on a single rank DIMM with a single clock pair—except for MAX 10, which doesn't support DIMMs.
  12. DQS SE is single-ended DQS.
  13. DQS DIFF is differential DQS

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