External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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12.3. Sequencer

The sequencer initializes and calibrates the external memory interface.

The UniPHY IP soft memory PHY supports an RTL-based sequencer and a Nios II-based sequencer for QDRII and QDRII+ SRAM, and RLDRAM II calibration.

The RTL-based sequencer performs FIFO calibration that includes adjusting the valid‑prediction FIFO (VFIFO) and latency FIFO (LFIFO) length. In addition to the FIFO calibration, the Nios II-based sequencer also performs I/O calibration that includes adjusting delay chains and phase settings to center-align the data pins with respect to the strobes that sample them. I/O calibration is required for memory interfaces running at higher frequencies to increase read and write margins.

Because the RTL-based sequencer performs a relatively simpler calibration process, it does not require a Nios II processor. For this reason, utilization of resources such as LEs and RAMs is lower than with the Nios II-based sequencer.

For more information about the RTL-based sequencer and Nios II-based sequencer, refer to the Functional Description—UniPHY chapter in volume 3 of the External Memory Interface Handbook .

For more information about the calibration process, refer to the “UniPHY Calibration Stages” section in the Functional Description—UniPHY chapter of the External Memory Interface Handbook.