External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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1.7. Document Revision History

Date Version Changes
March 2023 2023.03.06
  • Added subtitle to volume title.
  • Removed all Intel® Arria® 10 and Intel® Stratix® 10-related content.
  • Added note to top of Planning Pin and FPGA Resources topic.
May 2017 2017.05.08
  • Added Guidelines for Stratix 10 External Memory Interface IP, General Pin-Out Guidelines for Stratix 10 EMIF IP, and Resource Sharing Guidelines for Stratix 10 EMIF IP sections.
  • Rebranded as Intel.
October 2016 2016.10.31
  • Removed paragraph from Address and Command description in several pin utilization tables.
May 2016 2016.05.02
  • Modified Data Strobe and Address data in UDIMM, RDIMM, and LRDIMM Pin Options for DDR4 table in DDR, DDR2, DDR3, and DDR4 SDRAM DIMM Options. Added notes to table.
November 2015 2015.11.02
  • Changed instances of Quartus II to Quartus Prime.
  • Modified I/O Banks Selection, PLL Reference Clock and RZQ Pins Placement, and Ping Pong PHY Implementation sections in General Pin-Out Guidelines for Arria 10 EMIF IP.
  • Added Additional Requirements for DDR3 and DDR4 Ping-Pong PHY Interfaces in General Pin-Out Guidelines for Arria 10 EMIF IP.
  • Removed references to OCT Blocks from Resource Sharing Guidelines for Arria 10 EMIF IP section.
  • Added LPDDR3.
May 2015 2015.05.04
  • Removed the F672 package of the 10M25 device.
  • Updated the additional guidelines for MAX 10 devices to improve clarity.
  • Added related information link to the MAX 10 FPGA Signal Integrity Design Guidelines for the Additional Guidelines for MAX 10 Devices topic.
December 2014 2014.12.15
  • General Pin-Out Guidelines for Arria 10 EMIF IP section:
    • Added note to step 10.
    • Removed steps 13 and 14.
    • Added a bullet point to Address/Command Pins Location.
    • Added Ping Pong PHY Implementation
    • Added parenthetical comment to fifth bullet point in I/O Banks Selection
    • Added note following the procedure, advising that all pins in a DQS group should reside in the same I/O bank, for RLDRAM II and RLDRAM 3 interfaces.
  • Added QDR IV SRAM Clock Signals, QDR IV SRAM Commands and Addresses, AP, and AINV Signals, and QDR IV SRAM Data, DINV, and QVLD Signals topics.
  • Added note to Estimating Pin Requirements section.
  • DDR, DDR2, DDR3, and DDR4 SDRAM DIMM Options section:
    • Added UDIMM, RDIMM, and LRDIMM Pin Options for DDR4 table.
    • Changed notes to LRDIMM Pin Options for DDR, DDR2, and DDR3 table.
    • Removed reference to Chip ID pin.
August 2014 2014.08.15
  • Made several changes to Pin Counts for Various Example Memory Interfaces table:
    • Added DDR4 SDRAM and RLDRAM 3 CIO.
    • Removed x72 rows from table entries for DDR, DDR2, and DDR3.
    • Added Arria 10 to note 11.
    • Added notes 12-18.
  • Added DDR4 to descriptions of:
    • Clock signals
    • Command and address signals
    • Data, data strobe, DM/DBI, and optional ECC signals
    • SDRAM DIMM options
  • Added QDR II+ Xtreme to descriptions of:
    • SRAM clock signals
    • SRAM command signals
    • SRAM address signals
    • SRAM data, BWS, and QVLD signals
  • Changed title of section OCT Support for Arria II GX, Arria II GZ, Arria V, Arria V GZ, Cyclone V, Stratix III, Stratix IV, and Stratix V Devices to OCT Support.
  • Reorganized chapter to have separate sections for Guidelines for Arria 10 External Memory Interface IP and Guidelines for UniPHY-based External Memory Interface IP.
  • Revised Arria 10-specific guidelines.
December 2013 2013.12.16
  • Removed references to ALTMEMPHY and HardCopy.
  • Removed references to Cyclone III and Cyclone IV devices.
November 2012 6.0
  • Added Arria V GZ information.
  • Added RLDRAM 3 information.
  • Added LRDIMM information.
June 2012 5.0
  • Added LPDDR2 information.
  • Added Cyclone V information.
  • Added Feedback icon.
November 2011 4.0
  • Moved and reorganized Planning Pin and Resource section to Volume 2:Design Guidelines.

  • Added Additional Guidelines for Arria V GZ and Stratix V Devices section.
  • Added Arria V and Cyclone V information.
June 2011 3.0
  • Moved Select a Device and Memory IP Planning chapters to Volume 1.
  • Added information about interface pins.
  • Added guidelines for using PLL.
December 2010 2.1
  • Added a new section on controller efficiency.
  • Added Arria II GX and Stratix V information.
July 2010 2.0 Updated information about UniPHY-based interfaces and Stratix V devices.
April 2010 1.0 Initial release.