External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

7.3.4.3.1. Board Skew Parameters for LPDDR2/DDR2/DDR3 SDRAM

The following table lists board skew parameters for LPDDR2, DDR2, and DDR3 interfaces.
Table 79.  Parameter Descriptions

Parameter

Description

FPGA DQ/DQS Package Skews Deskewed on Board

Enable this parameter if you will deskew the FPGA package with your board traces on the DQ and DQS pins. This option increases the read capture and write margins. Enable this option when memory clock frequency is larger than 800 MHz. Enabling this option improves the read capture and write timing margin. You can also rely on the read capture and write timing margin in timing report to enable this option.

When this option is enabled, package skews are output on the DQ and DQS pins in the Pin-Out File (.pin) and package skew is not included in timing analysis. All of the other board delay and skew parameters related to DQ or DQS must consider the package and the board together. For more information, refer to DDR2 and DDR3 Board Layout Guidelines .

Address/Command Package Deskew

Enable this parameter if you will deskew the FPGA package with your board traces on the address and command pins. This option increases the address and command margins. Enable this option when memory clock frequency is larger than 800 MHz.Enabling this option will improve the address and command timing margin. You can also rely on the address and command margin in timing report to enable this option.

When this option is enabled, package skews are output on the address and command pins in the Pin-Out File (.pin) and package skew is not included in timing analysis. All of the other board delay and skew parameters related to Address and Command must consider the package and the board together. For more information, refer to DDR2 and DDR3 Board Layout Guidelines.

Maximum CK delay to DIMM/device

The delay of the longest CK trace from the FPGA to the memory device, whether on a DIMM or the same PCB as the FPGA is expressed by the following equation:



Where n is the number of memory clock and r is number rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clocks in each rank DIMM, the maximum CK delay is expressed by the following equation:

Maximum DQS delay to DIMM/device

The delay of the longest DQS trace from the FPGA to the memory device, whether on a DIMM or the same PCB as the FPGA is expressed by the following equation:



Where n is the number of DQS and r is number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 DQS in each rank DIMM, the maximum DQS delay is expressed by the following equation:

Minimum delay difference between CK and DQS

The minimum skew or smallest positive skew (or largest negative skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all DIMMs/devices is expressed by the following equation:



Where n is the number of memory clock, m is the number of DQS, and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the minimum delay difference between CK and DQS is expressed by the following equation:



This parameter value affects the write leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to non-leveling configurations of any number of ranks with the requirement that DQS must have positive margins in TimeQuest Report DDR.

For multiple boards, the minimum skew between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:



Note: If you are using a clamshell topology in a multirank/multi chip-select design with either DIMM or discrete devices, or using dual-die devices, the above calculations do not apply; you may use the default values in the GUI.

Maximum delay difference between CK and DQS

The maximum skew or smallest negative skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM/device over all DIMMs/devices is expressed by the following equation:



Where n is the number of memory clock, m is the number of DQS, and r is the number of rank of DIMM/device. For example in dual-rank DIMM implementation, if there are 2 pairs of memory clock and 4 DQS signals (two for each clock) for each rank DIMM, the maximum delay difference between CK and DQS is expressed by the following equation:

This value affects the write Leveling margin for DDR3 interfaces with leveling in multi-rank configurations. This parameter value also applies to non-leveling configurations of any number of ranks with the requirement that DQS must have positive margins in TimeQuest Report DDR.

For multiple boards, the maximum skew (or largest positive skew) between the CK signal and any DQS signal when arriving at the same DIMM over all DIMMs is expressed by the following equation, if you want to use the same design for several different boards:



Note: If you are using a clamshell topology in a multirank/multi chip-select design with either DIMM or discrete devices, or using dual-die devices, the above calculations do not apply; you may use the default values in the GUI.

Maximum skew within DQS group

The largest skew among DQ and DM signals in a DQS group. This value affects the read capture and write margins for DDR2 and DDR3 SDRAM interfaces in all configurations (single or multiple chip-select, DIMM or component).

For multiple boards, the largest skew between DQ and DM signals in a DQS group is expressed by the following equation:



Maximum skew between DQS groups

The largest skew between DQS signals in different DQS groups. This value affects the resynchronization margin in memory interfaces without leveling such as DDR2 SDRAM and discrete-device DDR3 SDRAM in both single- or multiple chip-select configurations. For protocols or families that do not have read resynchronization analysis, this parameter has no effect.

For multiple boards, the largest skew between DQS signals in different DQS groups is expressed by the following equation, if you want to use the same design for several different boards:



Average delay difference between DQ and DQS

The average delay difference between each DQ signal and the DQS signal, calculated by averaging the longest and smallest DQ signal delay values minus the delay of DQS. The average delay difference between DQ and DQS is expressed by the following equation:

where n is the number of DQS groups. For multi-rank or multiple CS configuration, the equation is:



Maximum skew within address and command bus

The largest skew between the address and command signals for a single board is expressed by the following equation:

For multiple boards, the largest skew between the address and command signals is expressed by the following equation, if you want to use the same design for several different boards:

Average delay difference between address and command and CK

A value equal to the average of the longest and smallest address and command signal delay values, minus the delay of the CK signal. The value can be positive or negative. Positive values represent address and command signals that are longer than CK signals; negative values represent address and command signals that are shorter than CK signals. The average delay difference between address and command and CK is expressed by the following equation:

where n is the number of memory clocks. For multi-rank or multiple CS configuration, the equation is:

The Quartus Prime software uses this skew to optimize the delay of the address and command signals to have appropriate setup and hold margins for DDR2 and DDR3 SDRAM interfaces. You should derive this value through board simulation.

For multiple boards, the average delay difference between address and command and CK is expressed by the following equation, if you want to use the same design for several different boards:



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