External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.6.7. PLL Usage for DDR3 SDRAM With Leveling Interfaces

The following table lists PLL usage for DDR3 protocols with leveling interfaces.
Table 24.  PLL Usage for DDR3 SDRAM With Leveling Interfaces

Clock

Stratix III and Stratix IV Devices

C0

  • phy_clk_1x in half-rate designs
  • aux_half_rate_clk
  • PLL scan_clk

C1

  • mem_clk_2x

C2

  • aux_full_rate_clk

C3

  • write_clk_2x

C4

  • resync_clk_2x

C5

  • measure_clk_1x

C6

  • ac_clk_1x

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