3.3.1. Comparison of DDR3 and DDR2 DQ and DQS ODT Features and Topology
The FPGA end (driver) I/O standard changes from SSTL18 for DDR2 to SSTL15 for DDR3, but all other OCT settings are identical. DDR3 offers enhanced ODT options for termination and drive-strength settings at the memory end of the line.
For more information, refer to the DDR3 SDRAM ODT matrix for writes and the DDR3 SDRAM ODT matrix for reads tables in the DDR2 and DDR3 SDRAM Board Design Guidelines chapter.
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