External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7. Implementing and Parameterizing Memory IP

The following topics describe the general overview of the IP core design flow to help you quickly get started with any IP core.

The IP Library is installed as part of the Quartus® Prime installation process.You can select and parameterize any Intel® IP core from the library. Intel provides an integrated parameter editor that allows you to customize IP cores to support a wide variety of applications. The parameter editor guides you through the setting of parameter values and selection of optional ports. The following section describes the general design flow and use of Intel® IP cores.

Note: Information for Arria® 10 External Memory Interface IP also applies to Arria® 10 External Memory Interface for HPS IP unless stated otherwise.

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