External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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Document Table of Contents

9. Analyzing Timing of Memory IP

The external memory physical layer (PHY) interface offers a combination of source-synchronous and self-calibrating circuits to maximize system timing margins. The physical layer interface is a plug‑and‑play solution that the Quartus® Prime TimeQuest Timing Analyzer timing constrains and analyzes.

The Intel FPGA IP and the numerous device features offered by Arria® II, Arria V, Intel Arria® 10, Cyclone® V, Stratix® III, Stratix IV, and Stratix V FPGAs, greatly simplify the implementation of an external memory interface.

This chapter details the various timing paths that determine overall external memory interface performance, and describes the timing constraints and assumptions that the PHY IP uses to analyze these paths.

This chapter focuses on timing constraints for external memory interfaces based on the UniPHY IP. For information about timing constraints and analysis of external memory interfaces and other source-synchronous interfaces based on the ALTDQ_DQS and ALTDQ_DQS2 IP cores, refer to AN 433: Constraining and Analyzing Source-Synchronous Interfaces and the Quartus® Prime TimeQuest Timing Analyzer chapter in volume 3 of the Quartus® Prime Handbook.

External memory interface timing analysis is supported only by the TimeQuest Timing Analyzer, for the following reasons:

  • The wizard-generated timing constraint scripts support only the TimeQuest analyzer.
  • The Classic Timing Analyzer does not offer analysis of source‑synchronous outputs. For example, write data, address, and command outputs.
  • The Classic Timing Analyzer does not support detailed rise and fall delay analysis.

The performance of an FPGA interface to an external memory device is dependent on the following items:

  • Read datapath timing
  • Write datapath timing
  • Address and command path timing
  • Clock to strobe timing (tDQSS in DDR and DDR2 SDRAM, and tKHK#H in QDR II and QDRII+ SRAM)
  • Read resynchronization path timing (applicable for DDR, DDR2, and DDR3 SDRAM in Arria II, Arria 10, Stratix III, Stratix IV, and Stratix V devices)
  • Write leveling path timing (applicable for DDR2 and DDR3 SDRAM with UniPHY, and DDR3 and DDR4 SDRAM with Arria 10 EMIF IP.)
  • PHY timing paths between I/O element and core registers
  • PHY and controller internal timing paths (core fMAX and reset recovery/removal)
  • I/O toggle rate
  • Output clock specifications
  • Bus turnaround timing (applicable for RLDRAM II and DDR2 and DDR3 SDRAM with UniPHY)
Note: External memory interface performance depends on various timing components, and overall system level performance is limited by performance of the slowest link (that is, the path with the smallest timing margins).

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