External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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9.8.5. PLL and Clock Network Assumptions for Stratix III Devices

To verify that the memory interface’s PLL is configured correctly, the following assumptions are necessary:
  • The PLL that generates the memory output clock signals and write data and clock signals must be set to No compensation mode to minimize output clock jitter.
  • The reference input clock signal to the PLL must be driven by the dedicated clock input pin located adjacent to the PLL, or from the clock output signal from the adjacent PLL. If the reference clock cascades from another PLL, that upstream PLL must be in No compensation mode and Low bandwidth mode.
  • For DDR3 and DDR2 SDRAM interfaces, use only regional or dual regional clock networks to route PLL outputs that generate the write data, write clock, and memory output clock signals. This requirement ensures that the memory output clocks (CK/CK#) meet the memory device input clock jitter specifications, and that output timing variations or skews are minimized.
  • For other memory types, the same clock tree type (global, regional, or dual regional) is recommended for PLL clocks generating the write clock, write data, and memory clock signals to minimize timing variations or skew between these outputs.