External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

8.2.6. UniPHY Abstract PHY Simulation

UniPHY IP generates both synthesizable and abstract models for simulation, with the abstract model as default. The UniPHY abstract model replaces the PLL with simple fixed-delay model, and the detailed models of the hard blocks with simple cycle-accurate functional models.

Full calibration mode cannot be used with abstract models, which is the default model type for all devices except Arria V and Cyclone V. In addition to enabling full calibration during generation, you must also disable the use of abstract models by modifying the generated simulation scripts as described below. For VHDL, the UniPHY abstract model is the only option because you cannot switch to regular simulation model. The PLL frequencies in simulation may differ from the real time simulation due to pico-second timing rounding.

However, you can switch to regular simulation models for Verilog HDL language. The full and quick calibration modes are available for regular simulation models.

Add an additional command line to the compilation script for the two relevant files to enable regular PHY simulation:

+define+ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL=0

The two relevant files are:

  • In <variation_name>_example_design/simulation/verilog/submodules:

    <variation_name>_example_sim_e0_if0_p0.sv

    and

    <variation_name>_example_sim_e0_if0_pll0.sv

or

  • In <variation_name>_sim/submodules:

    <variation_name>_p0.sv

    and

    <variation_name>_pll0.sv

To switch to regular simulation models for the Verilog HDL language on the example simulation design, follow the appropriate steps for your simulator:

  • For the Mentor simulator, edit the msim_setup.tcl file as follows:
    vlog 
    - sv "$QSYS_SIMDIR/submodules/<variation_name>_example_sim_e0_if0_p0.sv”
    +define+ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL=0
    -work <variation_name>_example_sim_work
    
    vlog - sv
    "$QSYS_SIMDIR/submodules/<variation_name>/_example_sim_e0_if0_pll0.sv"
    +define+ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL=0
    -work <variation_name>_example_sim_work
  • For the Cadence simulator, edit the ncsim_setup.sh file as follows:
    ncvlog
    - sv “$QSYS_SIMDIR/submodules/<variation_name>_example_sim_e0_if0_p0.sv"
    +define+ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL=0
    -work <variation_name>_example_sim_work
    - cdslib ./cds_libs/skip_example_sim_work.cds.lib
    ncvlog - sv 
    "$QSYS_SIMDIR/submodules/<variation_name>_example_sim_e0_if0_pll0.sv"
    +define+ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL=0
    -work <variation_name>_example_sim_work
    - cdslib ./cds_libs/<variation_name>_example_sim_work.cds.lib
    
  • For the Synopsys simulator, edit the vscmx_setup.sh file as follows:
    vlogan +v2k - sverilog
    "$QSYS_SIMDIR/submodules/<variation_name>_example_sim_e0_if0_p0.sv"
    +define+ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL=0
    - work <variation_name>_example_sim_work
    
    vlogan +v2k - sverilog
    "$QSYS_SIMDIR/submodules/<variation_name>_example_sim_e0_if0_pll0.sv"
    +define+ALTERA_ALT_MEM_IF_PHY_FAST_SIM_MODEL=0
    - work <variation_name>_example_sim_work

If you use the UniPHY abstract model, the simulation is two times faster in magnitude if compared to the real simulation model. Instantiating a standalone UniPHY IP in your design further improves the simulation time if you use a half-rate controller with UniPHY or a larger memory DQ width.

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