2.7.3. Length Matching Rules
Route all addresses and commands to match the clock signals to within ±20 ps to each discrete memory component. The following figure shows the DDR3 and DDR4 SDRAM component routing guidelines for address and command signals.
The timing between the DQS and clock signals on each device calibrates dynamically to meet tDQSS. The following figure shows the delay requirements to align DQS and clock signals. To ensure that the skew is not too large for the leveling circuit’s capability, follow these rules:
- Propagation delay of clock signal must not be shorter than propagation delay of DQS signal at every device:
CKi – DQSi > 0; 0 < i < number of components – 1
- Total skew of CLK and DQS signal between groups is less than one clock cycle:
(CKi + DQSi) max – (CKi + DQSi) min < 1 × tCK
Clk pair matching—If you are using a DIMM (UDIMM, RDIMM, or LRDIMM) topology, match the trace lengths up to the DIMM connector. If you are using discrete components, match the lengths for all the memory components connected in the fly-by chain.
DQ group length matching—If you are using a DIMM (UDIMM, RDIMM, or LRDIMM) topology, apply the DQ group trace matching rules described in the guideline table earlier up to the DIMM connector. If you are using discrete components, match the lengths up to the respective memory components.
When you are using DIMMs, it is assumed that lengths are tightly matched within the DIMM itself. You should check that appropriate traces are length-matched within the DIMM.
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