External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.5.5. Additional Guidelines for Arria V GZ and Stratix V Devices

This section provides guidelines for improving timing for Arria V GZ and Stratix V devices and the rules that you must follow to overcome timing failures.

Performing Manual Pin Placement

The following table lists rules that you can follow to perform proper manual pin placement and avoid timing failures.

The rules are categorized as follows:

  • Mandatory—This rule is mandatory and cannot be violated as it would result in a no‑fit error.
  • Recommended—This rule is recommended and if violated the implementation is legal but the timing is degraded.
  • Highly Recommended—This rule is not mandatory but is highly recommended because disregarding this rule might result in timing violations.
Table 16.  Manual Pin Placement Rules

Rules

Frequency

Device

Reason

Mandatory

Must place all CK, CK#, address, control, and command pins of an interface in the same I/O sub‑bank.

> 800 MHz

All

For optimum timing, clock and data output paths must share as much hardware as possible. For write data pins (for example, DQ/DQS), the best timing is achieved through the DQS Groups.

Must not split interface between top and bottom sides

Any

All

Because PLLs and DLLs on the top edge cannot access the bottom edge of a device and vice-versa.

Must not place pins from separate interfaces in the same I/O sub-banks unless the interfaces share PLL or DLL resources.

Any

All

All pins require access to the same leveling block.

Must not share the same PLL input reference clock unless the interfaces share PLL or DLL resources.

Any

All

Because sharing the same PLL input reference clock forces the same ff-PLL to be used. Each ff-PLL can drive only one PHY clock tree and interfaces not sharing a PLL cannot share a PHY clock tree.

Recommended

Place all CK, CK#, address, control, and command pins of an interface in the same I/O sub-bank.

<800 MHz

All

Place all CK/CK#, address, control, and command pins in the same I/O sub-bank when address and command timing is critical. For optimum timing, clock and data output paths should share as much hardware as possible. For write data pins (for example, DQ/DQS), the best timing is achieved through the DQS Groups.

Avoid using I/Os at the device corners (for example, sub-bank “A”).

Any

A7  (1)

The delay from the FPGA core fabric to the I/O periphery is higher toward the sub-banks in the corners. By not using I/Os at the device corners, you can improve core timing closure.

>=800 MHz

All

Corner I/O pins use longer delays, therefore avoiding corner I/O pins is recommended for better memory clock performance.

Avoid straddling an interface across the center PLL.

Any

All

Straddling the center PLL causes timing degradation, because it increases the length of the PHY clock tree and increases jitter. By not straddling the center PLL, you can improve core timing closure.

Use the center PLL(f-PLL1) for a wide interface that must straddle across center PLL.

>= 800 MHz

All

Using a non-center PLL results in driving a sub-bank in the opposite quadrant due to long PHY clock tree delay.

Place the DQS/DQS# pins such that all DQ groups of the same interface are next to each other and do not span across the center PLL.

Any

All

To ease core timing closure. If the pins are too far apart then the core logic is also placed apart which results in difficult timing closure.

Place CK, CK#, address, control, and command pins in the same quadrant as DQ groups for improved timing in general.

Any

All

Highly Recommended

Place all CK, CK#, address, control, and command pins of an interface in the same I/O sub-bank.

>= 800 MHz

All

For optimum timing, clock and data output paths should share as much hardware as possible. For write data pins (for example, DQ/DQS), the best timing is achieved through the DQS Groups.

Use center PLL and ensure that the PLL input reference clock pin is placed at a location that can drive the center PLL.

>= 800 MHz

All

Using a non-center PLL results in driving a sub-bank in the opposite quadrant due to long PHY clock tree delay.

If center PLL is not accessible, place pins in the same quadrant as the PLL.

>= 800 MHz

All

Note to Table:

  1. This rule is currently applicable to A7 devices only. This rule might be applied to other devices in the future if they show the same failure.

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