External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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2.2.4. Layout Guidelines for DDR2 SDRAM Interface

Unless otherwise specified, the following guidelines apply to the following topologies:
  • DIMM—UDIMM topology
  • DIMM—RDIMM topology
  • Discrete components laid out in UDIMM topology
  • Discrete components laid out in RDIMM topology

Trace lengths for CLK and DQS should tightly match for each memory component. To match the trace lengths on the board, a balanced tree topology is recommended for clock and address and command signal routing. In addition to matching the trace lengths, you should ensure that DDR timing is passing in the Report DDR Timing report. For Stratix devices, this timing is shown as Write Leveling tDQSS timing. For Arria and Cyclone devices, this timing is shown as CK vs DQS timing

For a table of device family topology support, refer to Leveling and Dynamic ODT.

The following table lists DDR2 SDRAM layout guidelines. These guidelines are Intel recommendations, and should not be considered as hard requirements. You should perform signal integrity simulation on all the traces to verify the signal integrity of the interface. You should extract the slew rate and propagation delay information, enter it into the IP and compile the design to ensure that timing requirements are met.

Note: The following layout guidelines also apply to DDR3 SDRAM without leveling interfaces.
Table 29.  DDR2 SDRAM Layout Guidelines   (1)

Parameter

Guidelines

DIMMs

If you consider a normal DDR2 unbuffered, unregistered DIMM, essentially you are planning to perform the DIMM routing directly on your PCB. Therefore, each address and control pin routes from the FPGA (single pin) to all memory devices must be on the same side of the FPGA.

General Routing

  • All data, address, and command signals must have matched length traces ± 50 ps.
  • All signals within a given Byte Lane Group should be matched length with maximum deviation of ±10 ps and routed in the same layer.

Clock Routing

  • A 4.7 K-ohm resistor to ground is recommended for each Clock Enable signal. You can place the resistor at either the memory end or the FPGA end of the trace.
  • Route clocks on inner layers with outer-layer run lengths held to under 500 mils (12.7 mm)
  • These signals should maintain a10-mil (0.254 mm) spacing from other nets
  • Clocks should maintain a length-matching between clock pairs of ±5 ps.
  • Differential clocks should maintain a length-matching between P and N signals of ±2 ps, routed in parallel.
  • Space between different pairs should be at least three times the space between the differential pairs and must be routed differentially (5-mil trace, 10‑15 mil space on centers), and equal to the signals in the Address/Command Group or up to 100 mils (2.54 mm) longer than the signals in the Address/Command Group.
  • Trace lengths for CLK and DQS should closely match for each memory component. To match trace lengths on the board, a balanced tree topology is recommended for clock and address and command signal routing. For Stratix device families, ensure that Write Leveling tDQSS is passing in the DDR timing report; for Arria and Cyclone device families, verify that CK vs DQS timing is passing in the DDR timing report.

Address and Command Routing

  • Unbuffered address and command lines are more susceptible to cross-talk and are generally noisier than buffered address or command lines. Therefore, un‑buffered address and command signals should be routed on a different layer than data signals (DQ) and data mask signals (DM) and with greater spacing.
  • Do not route differential clock (CK) and clock enable (CKE) signals close to address signals.

DQ, DM, and DQS Routing Rules

  • Keep the distance from the pin on the DDR2 DIMM or component to the termination resistor pack (VTT) to less than 500 mils for DQS[x] Data Groups.
  • Keep the distance from the pin on the DDR2 DIMM or component to the termination resistor pack (VTT) to less than 1000 mils for the ADR_CMD_CTL Address Group.
  • Parallelism rules for the DQS[x] Data Groups are as follows:
    • 4 mils for parallel runs < 0.1 inch (approximately 1× spacing relative to plane distance)
    • 5 mils for parallel runs < 0.5 inch (approximately 1× spacing relative to plane distance)
    • 10 mils for parallel runs between 0.5 and 1.0 inches (approximately 2× spacing relative to plane distance)
    • 15 mils for parallel runs between 1.0 and 6.0 inch (approximately 3× spacing relative to plane distance)
  • Parallelism rules for the ADR_CMD_CTL group and CLOCKS group are as follows:
    • 4 mils for parallel runs < 0.1 inch (approximately 1× spacing relative to plane distance)
    • 10 mils for parallel runs < 0.5 inch (approximately 2× spacing relative to plane distance)
    • 15 mils for parallel runs between 0.5 and 1.0 inches (approximately 3× spacing relative to plane distance)
    • 20 mils for parallel runs between 1.0 and 6.0 inches (approximately 4× spacing relative to plane distance)
  • All signals are to maintain a 20-mil separation from other, non‑related nets.
  • All signals must have a total length of < 6 inches.
  • Trace lengths for CLK and DQS should closely match for each memory component. To match trace lengths on the board, a balanced tree topology is recommended for clock and address and command signal routing. For Stratix device families, ensure that Write Leveling tDQSS is passing in the DDR timing report; for Arria and Cyclone device families, verify that CK vs DQS timing is passing in the DDR timing report.

Termination Rules

  • When pull-up resistors are used, fly-by termination configuration is recommended. Fly-by helps reduce stub reflection issues.
  • Pull-ups should be within 0.5 to no more than 1 inch.
  • Pull up is typically 56-ohms.
  • If using resistor networks:
  • Do not share R-pack series resistors between address/command and data lines (DQ, DQS, and DM) to eliminate crosstalk within pack.
  • Series and pull up tolerances are 1–2%.
  • Series resistors are typically 10 to 20-ohm.
  • Address and control series resistor typically at the FPGA end of the link.
  • DM, DQS, DQ series resistor typically at the memory end of the link (or just before the first DIMM).
  • If termination resistor packs are used:
  • The distance to your memory device should be less than 750 mils.
  • The distance from your FPGA device should be less than 1250 mils.

Quartus Prime Software Settings for Board Layout

  • To perform timing analyses on board and I/O buffers, use third party simulation tool to simulate all timing information such as skew, ISI, crosstalk, and type the simulation result into the UniPHY board setting panel.
  • Do not use advanced I/O timing model (AIOT) or board trace model unless you do not have access to any third party tool. AIOT provides reasonable accuracy but tools like HyperLynx provides better result. In operations with higher frequency, it is crucial to properly simulate all signal integrity related uncertainties.
  • The Quartus Prime software does timing check to find how fast the controller issues a write command after a read command, which limits the maximum length of the DQ/DQS trace. Check the turnaround timing in the Report DDR timing report and ensure the margin is positive before board fabrication. Functional failure happens if the margin is less than 0.

Note to Table:

  1. For point-to-point and DIMM interface designs, refer to the Micron website, www.micron.com.
Figure 20. Balanced Tree Topology


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