External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

5.2. RLDRAM 3 Configurations

The RLDRAM 3 UniPHY IP supports interfaces for CIO RLDRAM 3 with one or two devices. With two devices, the interface supports a width expansion configuration up to 72-bits. The termination and layout principles for SIO RLDRAM 3 interfaces are similar to CIO RLDRAM 3, except that SIO RLDRAM 3 interfaces have unidirectional data buses.

The following figure shows the main signal connections between the FPGA and a single CIO RLDRAM 3 component.

Figure 54. Configuration with a Single CIO RLDRAM 3 Component


Notes to Figure:

  1. Use external differential termination on CK/CK#.
  2. Use FPGA parallel on-chip termination (OCT) for terminating QK/QK# and DQ on reads.
  3. Use RLDRAM 3 component on-die termination (ODT) for terminating DQ, DM, and DK, DK# on writes.
  4. Use external discrete termination with fly-by placement to avoid stubs.
  5. Use external discrete termination for this signal, as shown for REF.
  6. Use external discrete termination, as shown for REF, but you may require a pull-up resistor to VDD as an alternative option. Refer to the RLDRAM 3 device data sheet for more information about RLDRAM 3 power-up sequencing.

The following figure shows the main signal connections between the FPGA and two CIO RLDRAM 3 components in a width expansion configuration.

Figure 55. Configuration with Two CIO RLDRAM 3 Components in a Width Expansion Configuration


Notes to Figure:

  1. Use FPGA parallel OCT for terminating QK/QK# and DQ on reads.
  2. Use RLDRAM 3 component ODT for terminating DQ, DM, and DK on writes.
  3. Use external dual 200 Ω differential termination.
  4. Use external discrete termination at the trace split of the balanced T or Y topology.
  5. Use external discrete termination at the trace split of the balanced T or Y topology, but you may require a pull-up resistor to VDD as an alternative option. Refer to the RLDRAM 3 device data sheet for more information about RLDRAM 3 power-up sequencing.

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