External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.16.2. Performing Advanced I/O Timing Analysis with Board Trace Delay Model

You should use this method only if you are unable to perform post-layout simulation on the memory interface signals to obtain the slew rate parameters, and/or when no simulation tool is available.

To perform I/O timing analysis using board trace delay model, follow these steps:

  1. After the instantiation is complete, analyze and synthesize your design.
  2. Add pin and DQ group assignment by running the <variation_name>_p0_pin_assignments.tcl script.
    Note: The naming of the pin assignment file may vary depending on the Quartus Prime software version that you are using.
  3. Enter the pin location assignments.
  4. Assign the virtual pins, if necessary.
  5. Enter the board trace model information. To enter board trace model information, follow these steps:
    1. In the Pin Planner, select the pin or group of pins for which you want to enter board trace parameters.
    2. Right-click and select Board Trace Model.
  6. Compile your design. To compile the design, on the Processing menu, click Start Compilation.
  7. After successfully compiling the design, perform timing analysis in the TimeQuest timing analyzer. To perform timing analysis, follow these steps:
    1. In the Quartus Prime software, on the Tools menu, click TimeQuest Timing Analyzer.
    2. On the Tasks pane, click Report DDR.
    3. On the Report pane, select Advanced I/O Timing>Signal Integrity Metrics.
    4. In the Signal Integrity Metrics window, right-click and select Regenerate to regenerate the signal integrity metrics.
    5. In the Signal Integrity Metrics window, note the 10–90% rise time (or fall time if fall time is worse) at the far end for CK/CK#, address, and command, DQS/DQS#, and DQ signals.
    6. In the DDR3 SDRAM controller parameter editor, in the Board Settings tab, type the values you obtained from the signal integrity metrics.
    7. For the board skew parameters, set the maximum skew within DQS groups of your design. Set the other board parameters to 0 ns.
    8. Compile your design.

Did you find the information on this page useful?

Characters remaining:

Feedback Message