External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.6.1.4.1. Stratix III

This topic details the timing margins, such as the read data and write data timing paths, which the TimeQuest Timing Analyzer callates for Stratix III designs. Timing paths internal to the FPGA are either guaranteed by design and tested on silicon, or analyzed by the TimeQuest Timing Analyzer using corresponding timing constraints.

For design guidelines about implementing and analyzing your external memory interface using the PHY in Stratix III and Stratix IV devices, refer to the design tutorials on the List of designs using Intel FPGA External Memory IP page of www.alterawiki.com.

Timing margins for chip-to-chip data transfers can be defined as:

Margin = bit period – transmitter uncertainties – receiver requirements

where:

  • Sum of all transmitter uncertainties = transmitter channel-to-channel skew (TCCS).

    The timing difference between the fastest and slowest output edges on data signals, including tCO variation, clock skew, and jitter. The clock is included in the TCCS measurement and serves as the time reference.

  • Sum of all receiver requirements = receiver sampling window (SW) requirement.

    The period of time during which the data must be valid to capture it correctly. The setup and hold times determine the ideal strobe position within the sampling window.

  • Receiver skew margin (RSKM) = margin or slack at the receiver capture register.

For TCCS and SW specifications, refer to the DC and Switching Characteristics chapter of the Stratix III Device Handbook.

The following figure relates this terminology to a timing budget diagram.

Figure 72. Sample Timing Budget Diagram


The timing budget regions marked “½ × TCCS” represent the latest data valid time and earliest data invalid times for the data transmitter. The region marked sampling window is the time required by the receiver during which data must stay stable. This sampling window comprises the following:

  • Internal register setup and hold requirements
  • Skew on the data and clock nets within the receiver device
  • Jitter and uncertainty on the internal capture clock
Note: The sampling window is not the capture margin or slack, but instead the requirement from the receiver. The margin available is denoted as RSKM.

The simple example illustrated in the preceding figure does not consider any board level uncertainties, assumes a center-aligned capture clock at the middle of the receiver sampling window region, and assumes an evenly distributed TCCS with respect to the transmitter clock pin. In this example, the left end of the bit period corresponds to time t = 0, and the right end of the bit period corresponds to time t = TUI (where TUI stands for time unit interval). Therefore, the center-aligned capture clock at the receiver is best placed at time t = TUI/2.

Therefore:

the total margin = 2 × RSKM = TUI – TCCS – SW.

Consider the case where the clock is not center-aligned within the bit period (clock phase shift = P), and the transmitter uncertainties are unbalanced (TCCSLEAD and TCCSLAG). TCCSLEAD is defined as the skew between the clock signal and latest data valid signal. TCCSLAG is defined as the skew between the clock signal and earliest data invalid signal. Also, the board level skew across data and clock traces are specified as tEXT. For this condition, you should compute independent setup and hold margins at the receiver (RSKMSETUP and RSKMHOLD). In this example, the sampling window requirement is split into a setup side requirement (SWSETUP) and hold side (SWHOLD) requirement. The following figure illustrates the timing budget for this condition. A timing budget similar to that shown is used for Stratix III FPGA read and write data timing paths.

Figure 73. Sample Timing Budget with Unbalanced (TCCS and SW) Timing Parameters


Therefore:

Setup margin = RSKMSETUP = P – TCCSLEAD – SWSETUP – tEXT

Hold margin = RSKMHOLD = (TUI – P) – TCCSLAG – SWHOLD – tEXT

The timing budget illustrated in the first figure with balanced timing parameters applies for calibrated paths where the clock is dynamically center-aligned within the data valid window. The timing budget illustrated in the second figure with unbalanced timing parameters applies for circuits that employ a static phase shift using a DLL or PLL to place the clock within the data valid window.

Did you find the information on this page useful?

Characters remaining:

Feedback Message