External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

12.4. PLL, DLL and OCT Resource Sharing

By default, each external memory interface in a device needs one PLL, one DLL, and one OCT control block. The number of PLL, DLL and OCT resources in a device is fixed; however, these resources can be shared by two or more memory interfaces when certain criteria are met. This method allows more memory interfaces to fit into a device and allows the remaining resources to be used for other purposes.

By sharing PLLs, fewer PLLs are used, and the number of clock networks and clock input pins required is also reduced. To share PLLs, the memory interfaces must meet the following criteria:

  • Run the same memory protocol (for example, DDR3 SDRAM)
  • Run at the same frequency
  • The controllers or PHYs run at the same rate (for example, half rate)
  • Use the same phase requirements (for example, additional core-to-periphery clock phase of 90°)
  • The memory interfaces are located on the same side of the device, or adjacent sides of the device if the PLL is able to drive both sides.

Intel® devices have up to four DLLs available to perform phase shift on the DQS signal for capturing the read data. The DLLs are located at the device corners and some of the DLLs can access two adjacent sides of the device. To share DLLs, the memory interfaces must meet the following criteria:

  • Run at the same frequency
  • The memory interfaces are located on the same side of the device, or adjacent sides of the device accessible by the DLL.

Memory interface pins with OCT calibration require the OCT control block to calibrate the OCT resistance value. Depending on the device family, the OCT control block uses either the RUP and RDN, or RZQ pins for OCT calibration. Each OCT control block can only be shared by pins powered by the same VCCIO level. Sharing of the OCT control block by interfaces operating at the same VCCIO level allows other OCT control blocks in the device to support other VCCIO levels. The unused RUP/RDN or RZQ pins can also be used for other purposes. For example, the RUP/RDN pins can be used as DQ or DQS pins. To share an OCT control block, the memory interfaces must operate at the same VCCIO level.

For more information about the resources required for memory interfaces in various device families, refer to the Planning Pin and FPGA Resources chapter.

For more information about how to share PLL, DLL and OCT control blocks, refer to the Functional Description—UniPHY chapter in volume 3 of the External Memory Interface Handbook .

For more information about the DLL, refer to the external memory interface chapters in the respective device handbooks.

For more information about the OCT control block, refer to the I/O features chapters in the respective device handbooks.

Did you find the information on this page useful?

Characters remaining:

Feedback Message