External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.6.1.10. Bus Turnaround Time

In DDR2 and DDR3 SDRAM, and RLDRAM II (CIO) with UniPHY designs that use bidirectional data bus, you may have potential encounter with data bus contention failure when a write command follows a read command. The bus-turnaround time analysis determines how much margin there is on the switchover time and prevents bus contention.

If the timing is violated, you can either increase the controller's bus turnaround time, which may reduce efficiency or board traces delay. Refer to <variation> _report_timing_core.tcl for the equation. You can find this analysis in the timing report. This analysis is only available for DDR2/3 SDRAM and RLDRAM II UniPHY IPs in Arria II GZ, Arria V, Cyclone V, Stratix IV, and Stratix V devices.

To determine whether the bus turnaround time issue is the cause of your design failure and to overcome this timing violation, follow these steps:

  1. When the design fails, change the default values of MEM_IF_WR_TO_RD_TURNAROUND_OCT and MEM_IF_RD_TO_WR_TURNAROUND_OCT parameters in the controller wrapper file to a maximum value of 5. If the design passes after the change, it is a bus turnaround issue.
  2. To solve the bus turnaround time issue, reduce the values of the MEM_IF_WR_TO_RD_TURNAROUND_OCT and MEM_IF_RD_TO_WR_TURNAROUND_OCT parameters gradually until you reach the minimum value needed for the design to pass on board.

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