External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.2.1.2. Specifying Parameters for the IP Catalog Flow

To specify parameters with the IP Catalog design flow, perform the following steps:
  1. In the Quartus Prime software, create a Quartus Prime project using the New Project Wizard available from the File menu.
  2. Launch the IP Catalog from the Tools menu.
  3. Select an external memory interface IP from the Memory Interfaces and Controllers folder in the Library list.
    Note: The availability of external memory interface IP depends on the device family your design is using.
  4. Depending on the window which appears, proceed as follows:
    • New IP Instance Window: Specify the Top-level Name and Device Settings, and click Ok.
    • Save IP Variation window: Specify the IP variation file name and IP variation file type, and click Ok.
  5. In the Presets window, select the preset matching your design requirement, and click Apply.
    Tip: If none of the presets match your design requirements, you can apply the closest preset available and then change the parameters manually. This method may be faster than entering all the parameters manually, and reduces the chance of having incorrect settings.
  6. Specify the parameters on all tabs.
    Note:
    • For detailed explanation of the parameters, refer to Parameterizing Memory Controllers with UniPHY IP and Parameterizing Memory Controllers with Arria 10 External Memory Interface IP.
    • Although you have applied presets, you may need to modify some of the preset parameters depending on the frequency of operation. A typical list of parameters which you might need to change includes the Memory CAS Latency setting, the Memory CAS Write Latency setting, and the tWTR, tFAW, tRRD, and tRTP settings.
    Tip:
    • As a good practice, review any warning messages displayed in the Messages Window and correct any errors before making further changes.
    • To simplify future work, you might want to store the current configuration by saving your own presets. To create, modify, or remove your own custom presets, click New, Update, or Delete at the bottom of the Presets list.
    • If you want to generate an example design for your current configuration, click Example Design at the top-right corner of the parameter editor, specify a path for the example design, and click Ok.
  7. Depending on which external memory interface IP is selected, perform the following steps to complete the IP generation:
    • For Arria® 10 or Stratix® 10 External Memory Interface IP:
      1. Click Finish. Your configuration is saved as a .qsys file.
      2. Click Yes when you are prompted to generate your IP.
      3. Set Create HDL design files for synthesis to Verilog or VHDL.
        Tip: If you want to do RTL simulation of your design, you should set Create simulation model to either Verilog or VHDL. Some RTL simulation-related files, including simulator-specific scripts, are generated only if you specify this parameter.
        Note: For Arria 10 External Memory Interface IP, the synthesis and simulation model files are identical. However, there are some differences in file types when generating for VHDL. For synthesis files, only the top-level wrapper is generated in VHDL; the other files are generated in System Verilog. For simulation files, all the files are generated as a Mentor-tagged encrypted IP for VHDL-only simulator support.
      4. Click Generate.
      5. When generation has completed, click Finish.
    • For UniPHY-based IP:
      1. Click the Finish button.
        Note: The Finish button may be unavailable until you have corrected all parameterization errors listed in the Messages window.
      2. If prompted, specify whether you want to generate an example design by checking or unchecking Generate Example Design, and then click Generate.
        CAUTION:
        If you have already generated an example design, uncheck Generate Example Design to prevent your previously generated files from being overwritten.
      3. When generation is completed, click Exit.
  8. Click Yes if you are prompted to add the .qip to the current Quartus Prime project. You can also turn on Automatically add Quartus Prime IP Files to all projects.
    Tip: Always read the generated readme.txt file, which contains information and guidelines specific to your configuration.
  9. You can now integrate your custom IP core instance in your design, simulate, and compile. While integrating your IP core instance into your design, you must make appropriate pin assignments. You can create a virtual pin to avoid making specific pin assignments for top-level signals while you are simulating and not ready to map the design to hardware.
Note: For information about the Quartus Prime software, including virtual pins and the IP Catalog and Qsys, refer to Quartus Prime Help.

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