External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families
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2.1. Leveling and Dynamic Termination
Intel recommends that for full DDR3 SDRAM compatibility when using discrete DDR3 SDRAM components, you should mimic the JEDEC DDR3 fly-by topology on your custom printed circuit boards (PCB).
Device |
I/O Support |
---|---|
Arria II |
Non-leveling |
Arria V GX, Arria V GT, Arria V SoC |
Non-leveling |
Arria V GZ |
Leveling |
Cyclone V GX, Cyclone V GT, Cyclone V SoC |
Non-leveling |
Stratix III |
Leveling |
Stratix IV |
Leveling |
Stratix V |
Leveling |