External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
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2.1. Leveling and Dynamic Termination

DDR3 SDRAM DIMMs, as specified by JEDEC, always use a fly-by topology for the address, command, and clock signals.

Intel recommends that for full DDR3 SDRAM compatibility when using discrete DDR3 SDRAM components, you should mimic the JEDEC DDR3 fly-by topology on your custom printed circuit boards (PCB).

Note: Arria® II, Arria V GX, Arria V GT, Arria V SoC, Cyclone® V, and Cyclone V SoC devices do not support DDR3 SDRAM with read or write leveling, so these devices do not support standard DDR3 SDRAM DIMMs or DDR3 SDRAM components using the standard DDR3 SDRAM fly-by address, command, and clock layout topology.
Table 24.  Device Family Topology Support 

Device

I/O Support

Arria II

Non-leveling

Arria V GX, Arria V GT, Arria V SoC

Non-leveling

Arria V GZ

Leveling

Cyclone V GX, Cyclone V GT, Cyclone V SoC

Non-leveling

Stratix III

Leveling

Stratix IV

Leveling

Stratix V

Leveling