External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

2.3.2. Terminations for Multi-Rank DDR3 SDRAM Unbuffered DIMM

You can implement a DDR3 SDRAM UDIMM interface in several permutations, such as single DIMM or multiple DIMMs, using either single-ranked or dual‑ranked UDIMMs. In addition to the UDIMM’s form factor, these termination recommendations are also valid for small‑outline (SO) DIMMs and MicroDIMMs.

The following table lists the different permutations of a two‑slot DDR3 SDRAM interface and the recommended ODT settings on both the memory and controller when writing to memory.

Table 31.  DDR3 SDRAM ODT Matrix for Writes (1) (2)  

Slot 1

Slot 2

Write To

Controller OCT  (3)

Slot 1

Slot 2

Rank 1

Rank 2

Rank 1

Rank 2

DR

DR

Slot 1

Series 50-ohm

120-ohm  (4)

ODT off

ODT off

40-ohm  (4)

Slot 2

Series 50-ohm

ODT off

40-ohm  (4)

120-ohm  (4)

ODT off

SR

SR

Slot 1

Series 50-ohm

120-ohm  (4)

Unpopulated

40-ohm  (4)

Unpopulated

Slot 2

Series 50-ohm

40-ohm  (4)

Unpopulated

120-ohm  (4)

Unpopulated

DR

Empty

Slot 1

Series 50-ohm

120-ohm  (4)

ODT off

Unpopulated

Unpopulated

Empty

DR

Slot 2

Series 50-ohm

Unpopulated

Unpopulated

120-ohm  (4)

ODT off

SR

Empty

Slot 1

Series 50-ohm

120-ohm  (4)

Unpopulated

Unpopulated

Unpopulated

Empty

SR

Slot 2

Series 50-ohm

Unpopulated

Unpopulated

120-ohm  (4)

Unpopulated

Notes to Table:

  1. SR: single-ranked DIMM; DR: dual-ranked DIMM.
  2. These recommendations are taken from the DDR3 ODT and Dynamic ODT session of the JEDEC DDR3 2007 Conference, Oct 3-4, San Jose, CA.
  3. The controller in this case is the FPGA.
  4. Dynamic ODT is required. For example, the ODT of Slot 2 is set to the lower ODT value of 40-ohms when the memory controller is writing to Slot 1, resulting in termination and thus minimizing any reflection from Slot 2. Without dynamic ODT, Slot 2 will not be terminated.

The following table lists the different permutations of a two‑slot DDR3 SDRAM interface and the recommended ODT settings on both the memory and controller when reading from memory.

Table 32.  DDR3 SDRAM ODT Matrix for Reads (1) (2)  

Slot 1

Slot 2

Read From

Controller OCT  (3)

Slot 1

Slot 2

Rank 1

Rank 2

Rank 1

Rank 2

DR

DR

Slot 1

Parallel 50-ohm

ODT off

ODT off

ODT off

40-ohm  (4)

Slot 2

Parallel 50-ohm

ODT off

40-ohm  (4)

ODT off

ODT off

SR

SR

Slot 1

Parallel 50-ohm

ODT off

Unpopulated

40-ohm  (4)

Unpopulated

Slot 2

Parallel 50-ohm

40-ohm  (4)

Unpopulated

ODT off

Unpopulated

DR

Empty

Slot 1

Parallel 50-ohm

ODT off

ODT off

Unpopulated

Unpopulated

Empty

DR

Slot 2

Parallel 50-ohm

Unpopulated

Unpopulated

ODT off

ODT off

SR

Empty

Slot 1

Parallel 50-ohm

ODT off

Unpopulated

Unpopulated

Unpopulated

Empty

SR

Slot 2

Parallel 50-ohm

Unpopulated

Unpopulated

ODT off

Unpopulated

Notes to Table:

  1. SR: single-ranked DIMM; DR: dual-ranked DIMM.
  2. These recommendations are taken from the DDR3 ODT and Dynamic ODT session of the JEDEC DDR3 2007 Conference, Oct 3-4, San Jose, CA.
  3. The controller in this case is the FPGA. JEDEC typically recommends 60-ohms, but this value assumes that the typical motherboard trace impedance is 60-ohms and that the controller supports this termination. Intel recommends using a 50-ohm parallel OCT when reading from the memory.

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