External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

5.1. RLDRAM II Configurations

The RLDRAM II Controller with UniPHY IP supports CIO RLDRAM II interfaces with one or two devices. With two devices, the interface supports a width expansion configuration up to 72-bits. The termination and layout principles for SIO RLDRAM II interfaces are similar to CIO RLDRAM II, except that SIO RLDRAM II interfaces have unidirectional data buses.

The following figure shows the main signal connections between the FPGA and a single CIO RLDRAM II component.

Figure 52. Configuration with a Single CIO RLDRAM II Component


Notes to Figure:

  1. Use external differential termination on DK/DK# and CK/CK#.
  2. Use FPGA parallel on-chip termination (OCT) for terminating QK/QK# and DQ on reads.
  3. Use RLDRAM II component on-die termination (ODT) for terminating DQ and DM on writes.
  4. Use external discrete termination with fly-by placement to avoid stubs.
  5. Use external discrete termination for this signal, as shown for REF.
  6. Use external discrete termination, as shown for REF, but you may require a pull-up resistor to VDD as an alternative option. Refer to the RLDRAM II device data sheet for more information about RLDRAM II power-up sequencing.

The following figure shows the main signal connections between the FPGA and two CIO RLDRAM II components in a width expansion configuration.

Figure 53. Configuration with Two CIO RLDRAM II Components in a Width Expansion Configuration


Notes to Figure:

  1. Use external differential termination on DK/DK#.
  2. Use FPGA parallel on-chip termination (OCT) for terminating QK/QK# and DQ on reads.
  3. Use RLDRAM II component on-die termination (ODT) for terminating DQ and DM on writes.
  4. Use external dual 200 Ω differential termination.
  5. Use external discrete termination at the trace split of the balanced T or Y topology.
  6. Use external discrete termination at the trace split of the balanced T or Y topology, but you may require a pull-up resistor to VDD as an alternative option. Refer to the RLDRAM II device data sheet for more information about RLDRAM II power-up sequencing.

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