External Memory Interface Handbook Volume 2: Design Guidelines

ID 683385
Date 5/08/2017
Document Table of Contents

4.1.2. OCT Signal Terminations for Arria V and Cyclone V Devices

Arria V and Cyclone V devices offer OCT technology. The following table lists the extent of OCT support for each device.
Table 38.  On-Chip Termination Schemes 

Termination Scheme

I/O Standard

Arria V and Cyclone V

On-Chip Series Termination without Calibration



On-Chip Series Termination with Calibration



On-chip series (RS) termination supports output buffers, and bidirectional buffers only when they are driving output signals. LPDDR2 SDRAM interfaces have bidirectional data paths. The UniPHY IP uses series OCT for memory writes but no parallel OCT for memory reads because Arria V and Cyclone V support only on-chip series termination in the HSUL-12 I/O standard.

For Arria V and Cyclone V devices, the HSUL-12 I/O calibrated terminations are calibrated against 240 ohm 1% resistors connected to the RZQ pins in an I/O bank with the same VCCIO as the LPDDR2 interface.

Calibration occurs at the end of the device configuration.

LPDDR2 SDRAM memory components have a ZQ pin which connects through a resistor RZQ (240 ohm) to ground. The output signal impedances for LPDDR2 SDRAM are 34.3 ohm, 40 ohm, 48 ohm, 60 ohm, 80 ohm, and 120 ohm. The output signal impedance is set by mode register during initialization. Refer to the LPDDR2 SDRAM device data sheet for more information.

For information about OCT, refer to the I/O Features in Arria V Devices chapter in the Arria V Device Handbook, or the I/O Features in Cyclone V Devices chapter in the Cyclone V Device Handbook.

The following section shows HyperLynx simulation eye diagrams to demonstrate signal termination options. Intel strongly recommends signal terminations to optimize signal integrity and timing margins, and to minimize unwanted emissions, reflections, and crosstalk.

All of the eye diagrams shown in this section are for a 50 ohm trace with a propagation delay of 509 ps which is approximately a 2.8-inch trace on a standard FR4 PCB. The signal I/O standard is HSUL-12.

The eye diagrams in this section show the best case achievable and do not take into account PCB vias, crosstalk, and other degrading effects such as variations in the PCB structure due to manufacturing tolerances.

Note: Simulate your design to ensure correct operation.

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