External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
Give Feedback Resynchronization Timing Margin

Observe the size and margins available for resynchronization using the debug toolkit or system console.

Refer to External Memory Interface Debug Toolkit chapter in volume 3 of the External Memory Interface Handbook.

Also, for PHY configurations that use a dedicated PLL clock phase (as opposed to a resynchronization FIFO buffer), use the same process as described in “Write Timing Margin”, to dynamically sweep resynchronization margin (c4 resynch_clk_2x).