10.7.2.1.4. Resynchronization Timing Margin
Refer to External Memory Interface Debug Toolkit chapter in volume 3 of the External Memory Interface Handbook.
Additionally for PHY configurations that use a dedicated PLL clock phase (as opposed to a resynchronization FIFO buffer), use the same process as described in “Write Timing Margin”, to dynamically sweep resynchronization margin (c4 resynch_clk_2x).
Did you find the information on this page useful?