8.2. Simulation Walkthrough with UniPHY IP
For a given design on a given board, the latency found may differ by one clock cycle (for full-rate designs) or two clock cycles (for half-rate designs) upon resetting the board. Different boards can also show different latencies even with the same design.
The UniPHY IP supports only functional simulation. Functional simulation is supported at the RTL level and after generating a post-fit functional simulation netlist. The post-fit netlist for designs that contain UniPHY IP is a hybrid of the gate level (for FPGA core) and RTL level (for the external memory interface IP). Intel recommends that you validate the functional operation of your design using RTL simulation, and the timing of your design using TimeQuest Timing Analysis.
For UniPHY-based external memory interfaces, you can perform functional simulation using an example design that is generated with your IP core. The example design files are created in the \<variation_name>_example_design directory.
You can use the IP functional simulation model with any supported VHDL or Verilog HDL simulator.
After you have generated the memory IP, view the README.txt file located in the \<variation_name>_example_design\simulation directory for instructions on how to generate the simulation example design for Verilog HDL or VHDL. The README.txt file also explains how to run simulation using the ModelSim* - Intel FPGA Edition software. Simulation scripts for the Mentor Graphics, Cadence, Aldec, and Synopsys simulators are provided; however, detailed instructions on how to perform simulation using these third-party simulators are not provided.
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