External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents
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6.2.1. Output from the FPGA to the QDR II SRAM Component

The following output signals are from the FPGA to the QDR II SRAM component:
  • write data
  • byte write select (BWSn)
  • address
  • control (WPSn and RPSn)
  • clocks, K/K#

Intel recommends that you terminate the write clocks, K and K#, with a single-ended fly-by 50-ohmparallel termination to VTT. However, simulations show that you can consider a differential termination if the clock pair is well matched and routed differentially.

Intel strongly recommends signal terminations to optimize signal integrity and timing margins, and to minimize unwanted emissions, reflections, and crosstalk.

For point-to-point signals, Intel recommends that you place a fly-by termination by terminating at the end of the transmission line after the receiver to avoid unterminated stubs. The guideline is to place the fly-by termination within 100 ps propagation delay of the receiver.

Although not recommended, you can place the termination before the receiver, which leaves an unterminated stub. The stub delay is critical because the stub between the termination and the receiver is effectively unterminated, causing additional ringing and reflections. Stub delays should be less than 50 ps.

Note: Simulate your design to ensure correct functionality.