External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.5. Pin Connection Guidelines Tables

The following table lists the FPGA pin utilization for DDR, DDR2, and DDR3 SDRAM without leveling interfaces.
Table 11.  FPGA Pin Utilization for DDR, DDR2, and DDR3 SDRAM without Leveling Interfaces

Interface Pin Description

Memory Device Pin Name

FPGA Pin Utilization

Arria II GX

Arria II GZ, Stratix III, and Stratix IV

Arria V, Cyclone V,
and Stratix V

MAX 10 FPGA

Memory System Clock

CK and CK#  (1)  (2)

If you are using single‑ended DQS signaling, place any unused DQ or DQS pins with DIFFOUT capability located in the same bank or on the same side as the data pins.

If you are using differential DQS signaling in UniPHY IP, place on DIFFOUT in the same single DQ group of adequate width to minimize skew.

If you are using single‑ended DQS signaling, place any DIFFOUT pins in the same bank or on the same side as the data pins

If you are using differential DQS signaling in UniPHY IP, place any DIFFOUT pins in the same bank or on the same side as the data pins. If there are multiple CK/CK# pairs, place them on DIFFOUT in the same single DQ group of adequate width.

For example, DIMMs requiring three memory clock pin-pairs must use a ×4 DQS group.

If you are using single‑ended DQS signaling, place any unused DQ or DQS pins with DIFFOUT capability in the same bank or on the same side as the data pins.

If you are using differential DQS signaling, place any unused DQ or DQS pins with DIFFOUT capability for the mem_clk[n:0] and mem_clk_n[n:0] signals (where n>=0). CK and CK# pins must use a pin pair that has DIFFOUT capability.

CK and CK# pins can be in the same group as other DQ or DQS pins. CK and CK# pins can be placed such that one signal of the differential pair is in a DQ group and the other signal is not.

If there are multiple CK and CK# pin pairs, place them on DIFFOUT in the same single DQ group of adequate width.

Place any differential I/O pin pair ( DIFFIO) in the same bank or on the same side as the data pins.

Clock Source

Dedicated PLL clock input pin with direct connection to the PLL (not using the global clock network).

For Arria II GX, Arria II GZ, Arria V GZ, Stratix III, Stratix IV and Stratix V Devices, also ensure that the PLL can supply the input reference clock to the DLL. Otherwise, refer to alternative DLL input reference clocks (see General Pin-out Guidelines).

Reset

Dedicated clock input pin to accommodate the high fan-out signal.

Data

DQ

DQ in the pin table, marked as Q in the Quartus Prime Pin Planner. Each DQ group has a common background color for all of the DQ and DM pins, associated with DQS (and DQSn) pins.

Data mask

DM

Data strobe

DQS or DQS and DQSn (DDR2 and DDR2 SDRAM only)

DQS (S in the Quartus Prime Pin Planner) for single-ended DQS signaling or DQS and DQSn (S and Sbar in the Quartus Prime Pin Planner) for differential DQS signaling. DDR2 supports either single-ended or differential DQS signaling. DDR3 SDRAM mandates differential DQS signaling.

Address and command

A[], BA[], CAS#, CKE, CS#, ODT, RAS#, WE#, RESET#

Any user I/O pin. To minimize skew, you must place the address and command pins in the same bank or side of the device as the CK/CK# pins, DQ, DQS, or DM pins. The reset# signal is only available in DDR3 SDRAM interfaces. Intel® devices use the SSTL-15 I/O standard on the RESET# signal to meet the voltage requirements of 1.5 V CMOS at the memory device. Intel® recommends that you do not terminate the RESET# signal to VTT.

Notes to Table:

  1. The first CK/CK# pair refers to mem_clk[0] or mem_clk_n[0] in the IP core.
  2. The restriction on the placement for the first CK/CK# pair is required because this placement allows the mimic path that the IP VT tracking uses to go through differential I/O buffers to mimic the differential DQS signals.

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