External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.5.2. QDR II and QDR II+ SRAM Pin Utilization for Arria II, Arria V, Stratix III, Stratix IV, and Stratix V Devices

The following table lists the FPGA pin utilization for QDR II and QDR II+ SRAM interfaces.
Table 13.  QDR II and QDR II+ SRAM Pin Utilization for Arria II, Arria V, Stratix III, Stratix IV, and Stratix V Devices

Interface Pin Description

Memory Device Pin Name

FPGA Pin Utilization

Read Clock

CQ and CQ#  (1)

For QDR II SRAM devices with 1.5 or 2.5 cycles of read latency or QDR II+ SRAM devices with 2.5 cycles of read latency, connect CQ to DQS pin (S in the Quartus Prime Pin Planner), and CQn to CQn pin (Qbar in the Quartus Prime Pin Planner).

For QDR II or QDR II+ SRAM devices with 2.0 cycles of read latency, connect CQ to CQn pin (Qbar in the Quartus Prime Pin Planner), and CQn to DQS pin (S in the Quartus Prime Pin Planner).

Arria V devices do not use CQn. The CQ rising and falling edges are used to clock the read data, instead of separate CQ and CQn signals.

Read Data

Q

DQ pins (Q in the Quartus Prime Pin Planner). Ensure that you are using the DQ pins associated with the chosen read clock pins (DQS and CQn pins). QVLD pins are only available for QDR II+ SRAM devices and note that Intel® FPGA IP does not use the QVLD pin.

Data Valid

QVLD

Memory and Write Data Clock

K and K#

Differential or pseudo-differential DQ, DQS, or DQSn pins in or near the write data group.

Write Data

D

DQ pins. Ensure that you are using the DQ pins associated with the chosen memory and write data clock pins (DQS and DQS pins).

Byte Write Select

BWS#, NWS#

Address and Command

A, WPS#, RPS#

Any user I/O pin. To minimize skew, you should place address and command pins in the same bank or side of the device as the following pins: K and K# pins, DQ, DQS, BWS#, and NWS# pins. If you are using burst-length-of-two devices, place the address signals in a DQS group pin as these signals are now double data rate.

Clock source

Dedicated PLL clock input pin with direct (not using a global clock net) connection to the PLL and optional DLL required by the interface.

Reset

Dedicated clock input pin to accommodate the high fan-out signal

Note to table:

  1. For Arria V designs with integer latency, connect the CQ# signal to the CQ/CQ# pins from the pin table and ignore the polarity in the Pin Planner. For Arria V designs with fractional latency, connect the CQ signal to the CQ/CQ# pins from the pin table.

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