External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.5.6. Additional Guidelines for Arria V ( Except Arria V GZ) Devices

This section provides guidelines on how to improve timing for Arria V devices and the rules that you must follow to overcome timing failures.

Performing Manual Pin Placement

The following table lists rules you can follow to perform proper manual pin placement and avoid timing failures.

The rules are categorized as follows:

  • Mandatory—This rule is mandatory and cannot be violated as it would result in a no‑fit error.
  • Recommended—This rule is recommended and if violated the implementation is legal but the timing is degraded.
Table 17.  Manual Pin Placement Rules for Arria V (Except Arria V GZ) Devices

Rules

Frequency

Device

Reason

Mandatory

Must place all CK, CK#, address, control, and command pins of an interface on the same device edge as the DQ groups.

All

All

For optimum timing, clock and data output ports must share as much hardware as possible.

Must not place pins from separate interfaces in the same I/O sub-banks unless the interfaces share PLL or DLL resources. To share resources, the interfaces must use the same memory protocol, frequency, controller rate, and phase requirements.

All

All

All pins require access to the same PLL/DLL block.

Must not split interface between top, bottom, and right sides.

All

All

PHYCLK network support interfaces at the same side of the I/O banks only. PHYCLK networks do not support split interface.

Recommended

Place the DQS/DQS# pins such that all DQ groups of the same interface are next to each other and do not span across the center PLL.

All

All

To ease core timing closure. If the pins are too far apart then the core logic is also placed apart which results in difficult timing closure.

Place all pins for a memory interface in an I/O bank and use the nearest PLL to that I/O bank for the memory interface.

All

All

Improve timing performance by reducing the PHY clock tree delay.

Note: Not all hard memory controllers on a given device package necessarily have the same address widths; some hard memory controllers have 16-bit address capability, while others have only 15-bit addresses.

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