External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
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5.3. Signal Terminations

The following table lists the on-chip series termination (RS OCT) and on-chip parallel termination (RT OCT) schemes for supported devices.
Note: For RLDRAM 3, the default output termination resistance (RS) changes from 50 ohm to 25 ohm with the release of the Quartus II software version 12.1 SP1.
Table 43.  On-Chip Termination Schemes 

Termination Scheme

Class I Signal Standards

FPGA Device

Arria II GZ, Stratix III, and Stratix IV

Arria V and Stratix V

Row/Column I/O

Row/Column I/O

RS OCT without Calibration

RLDRAM II - HSTL-15 and HSTL-18

RLDRAM 3 - HSTL 1.2 V

50

50

RS OCT with Calibration

RLDRAM II - HSTL-15 and HSTL-18

RLDRAM 3 - HSTL 1.2 V

50

50  (1)

RT OCT with Calibration

RLDRAM II - HSTL-15 and HSTL-18

RLDRAM 3 - HSTL 1.2 V

50

50  (1)

Note to Table:

  1. Although 50-ohms is the recommended option, Stratix V devices offer a wider range of calibrated termination impedances.

RLDRAM II and RLDRAM 3 CIO interfaces have bidirectional data paths. The UniPHY IP uses dynamic OCT on the datapath, which switches between series OCT for memory writes and parallel OCT for memory reads. The termination schemes also follow these characteristics:

  • Although 50 -ohm. is the recommended option, Stratix V devices offer a wider range of calibrated termination impedances.
  • RS OCT supports output buffers.
  • RT OCT supports input buffers.
  • RS OCT supports bidirectional buffers only when they are driving output signals.
  • RT OCT bidirectional buffers only when they are input signals.

For Arria II GZ, Stratix III, and Stratix IV devices, the HSTL Class I I/O calibrated terminations are calibrated against 50-ohm 1% resistors connected to the R UP and R DN pins in an I/O bank with the same VCCIO as the RLDRAM II interface. For Arria V and Stratix V devices, the HSTL Class I I/O calibrated terminations are calibrated against 100-ohm 1% resistors connected to the R ZQ pins in an I/O bank with the same VCCIO as the RLDRAM II and RLDRAM 3 interfaces.

The calibration occurs at the end of the device configuration.

RLDRAM II and RLDRAM 3 memory components have a ZQ pin that connects through a resistor RQ to ground. Typically the RLDRAM II and RLDRAM 3 output signal impedance is a fraction of R Q. Refer to the RLDRAM II and RLDRAM 3 device data sheets for more information.

For information about OCT, refer to the following:

  • I/O Features in Arria II Devices chapter in the Arria II Device Handbook
  • I/O Features in Arria V Devices chapter in the Arria V Device Handbook
  • Stratix III Device I/O Features chapter in the Stratix III Device Handbook
  • I/O Features in Stratix IV Devices chapter in the Stratix IV Device Handbook
  • I/O Features in Stratix V Devices chapter in the Stratix V Device Handbook

Intel strongly recommends signal terminations to optimize signal integrity and timing margins, and to minimize unwanted emissions, reflections, and crosstalk.

Note: Simulate your design to check your termination scheme.

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