9.1.4. Other FPGA Timing Parameters
I/O toggle rates vary based on speed grade, loading, and I/O bank location— top/bottom versus left/right. This toggle rate is also a function of the termination used (OCT or external termination) and other settings such as drive strength and slew rate.
For information about signal integrity, refer to the board design guidelines chapters and AN 476: Impact of I/O Settings on Signal Integrity in Stratix III Devices.
Output clock specifications include clock period jitter, half‑period jitter, cycle-to-cycle jitter, and skew between FPGA clock outputs. You can obtain these specifications from the FPGA data sheet and must meet memory device requirements. You can use these specifications to determine the overall data valid window for signals transmitted between the memory and FPGA device.
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