External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

12.5. Pin Placement Consideration

The Stratix® V, Arria® V, Cyclone® V, and MAX® 10 device families use the PHY clock (PHYCLK) networks to clock the external memory interface pins for better performance.

Each PHYCLK network is driven by a PLL.

  • In Cyclone V and Stratix V devices, the PHYCLK network spans across two I/O banks on the same side of the device.
  • For Arria V devices, each PHYCLK network spans across one I/O bank.
  • For MAX 10 devices, the PHYCLK network is available only for the I/O banks on the right side of the device.

All pins for a memory interface must be placed on the same side of the device.

For more information about pin placement guidelines related to the PHYCLK network, refer to the following documents:

  • External Memory Interfaces in Stratix V Devices chapter in volume 2 of the Stratix V Device Handbook
  • External Memory Interfaces in Arria V Devices chapter in volume 2 of the Arria V Device Handbook
  • External Memory Interfaces in Cyclone V Devices chapter in volume 2 of the Cyclone V Device Handbook
  • MAX 10 External Memory Interface Architecture and Features chapter of the MAX 10 External Memory Interface User Guide

Certain device families do not use the PHYCLK network to allow greater flexibility in pin placement. These device families support the following interface types:

  • Wraparound interfaces, in which data pins from a memory interface are placed on two adjacent sides of a device.
  • Split interfaces, in which data pins are place on two opposite I/O banks.

The x36 emulated mode is supported in certain device families that do not use the PHY clock network for QDRII and QDRII+ SRAM x36 interfaces. In x36 emulated mode, two x18 DQS groups or four x9 DQS groups can be combined to form a 36-bit wide write data bus. Also, two x18 DQS groups can be combined to form a 36-bit wide read data bus. This method allows a device to support x36 QDRII and QDRII+ SRAM interfaces even if the device does hot have the required number of x36 DQS groups.

Some device families might support wraparound or x36 emulated mode interfaces at slightly lower frequencies.

For information about the devices that support wraparound and x36 emulated mode interfaces, and the supported frequency for your design, refer to the External Memory Interface Spec Estimator page on www.altera.com.

For more information about x36 emulated mode support for QDRII and QDRII+ SRAM interfaces, refer to the Planning Pin and FPGA Resources chapter.

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