External Memory Interface Handbook Volume 2: Design Guidelines

Download
ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.1.3. LPDDR2 SDRAM Controller with UniPHY Interfaces

The following table lists the LPDDR2 SDRAM signals available for each interface in Qsys and provides a description and guidance on how to connect those interfaces.
Table 58.  LPDDR2 SDRAM Controller with UniPHY Interfaces

Signals in Interface

Interface Type

Description/How to Connect

pll_ref_clk interface

pll_ref_clk

Clock input

PLL reference clock input.

global_reset interface

global_reset_n

Reset input

Asynchronous global reset for PLL and all logic in PHY.

soft_reset interface

soft_reset_n

Reset input

Asynchronous reset input. Resets the PHY, but not the PLL that the PHY uses.

afi_reset interface

afi_reset_n

Reset output (PLL master/no sharing)

When the interface is in PLL master or no sharing modes, this interface is an asynchronous reset output of the AFI interface. The controller asserts this interface when the PLL loses lock or the PHY is reset.

afi_reset_export interface

afi_reset_export_n

Reset output (PLL master/no sharing)

This interface is a copy of the afi_reset interface. It is intended to be connected to PLL sharing slaves.

afi_reset_in interface

afi_reset_n

Reset input (PLL slave)

When the interface is in PLL slave mode, this interface is a reset input that you must connect to the afi_reset_export_n output of an identically configured memory interface in PLL master mode.

afi_clk interface

afi_clk

Clock output (PLL master/no sharing)

This AFI interface clock can be a full-rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL master or no sharing modes, this interface is a clock output.

afi_clk_in interface

afi_clk

Clock input (PLL slave)

This AFI interface clock can be a full-rate or half-rate memory clock frequency based on the memory interface parameterization. When the interface is in PLL slave mode, you must connect this afi_clk input to the afi_clk output of an identically configured memory interface in PLL master mode.

afi_half_clk interface

afi_half_clk

Clock output (PLL master/no sharing)

The AFI half clock that is half the frequency of afi_clk. When the interface is in PLL master or no sharing modes, this interface is a clock output.

afi_half_clk_in interface

afi_half_clk

Clock input (PLL slave)

The AFI half clock that is half the frequency of afi_clk. When the interface is in PLL slave mode, this is a clock input that you must connect to the afi_half_clk output of an identically configured memory interface in PLL master mode.

Memory interface

mem_ca

Conduit

Interface signals between the PHY and the memory device.

mem_ck

mem_ck_n

mem_cke

mem_cs_n

mem_dm

mem_dq

mem_dqs

mem_dqs_n

avl interface

avl_ready

Avalon-MM Slave

Avalon-MM interface signals between the memory interface and user logic.

avl_burst_begin

avl_addr

avl_rdata_valid

avl_rdata

avl_wdata

avl_be

avl_read_req

avl_write_req

avl_size

status interface

local_init_done

Conduit

Memory interface status signals.

local_cal_success

local_cal_fail

oct interface

rzq

Conduit

OCT reference resistor pins for rzqin.

local_powerdown interface

local_powerdn_ack

Conduit

This powerdown interface for the controller is enabled only when you turn on Enable Auto Powerdown.

local_deep_powerdn interface

local_deep_powerdn_ack

Conduit

Deep power down interface for the controller to enable deep power down. This interface is enable when turn on Enable Deep Power-Down Controls.

local_deep_powerdn_chip

local_deep_powerdn_req

pll_sharing interface

pll_mem_clk

Conduit

Interface signals for PLL sharing, to connect PLL masters to PLL slaves. This interface is enabled only when you set PLL sharing mode to master or slave.

pll_write_clk

pll_addr_cmd_clk

pll_locked

pll_avl_clk

pll_config_clk

pll_mem_phy_clk

afi_phy_clk

pll_write_clk_pre_phy_clk

dll_sharing interface

dll_delayctrl

Conduit

DLL sharing interface for connecting DLL masters to DLL slaves. This interface is enabled only when you set DLL sharing mode to master or slave.

dll_pll_locked

oct_sharing interface

seriesterminationcontrol

Conduit

OCT sharing interface for connecting OCT masters to OCT slaves. This interface is enabled only when you set OCT sharing mode to master or slave.

parallelterminationcontrol

autoprecharge_req interface

local_autopch_req

Conduit

Precharge interface for connection to a custom control block. This interface is enabled only when you turn on Auto-precharge Control.

user_refresh interface

local_refresh_req

Conduit

User refresh interface for connection to a custom control block. This interface is enabled only when you turn on User Auto-Refresh Control.

local_refresh_chip

local_refresh_ack

self_refresh interface

local_self_rfsh_req

Conduit

Self refresh interface for connection to a custom control block. This interface is enabled only when you turn on Self-refresh Control.

local_self_rfsh_chip

local_self_rfsh_ack

ecc_interrupt interface

ecc_interrupt

Conduit

ECC interrupt signal for connection to a custom control block. This interface is enabled only when you turn on Error Detection and Correction Logic.

csr interface

csr_write_req

Avalon-MM Slave

Configuration and status register signals for the memory interface, for connection to an Avalon_MM master. This interface is enabled only when you turn on Configuration and Status Register.

csr_read_req

csr_waitrequest

csr_addr

csr_be

csr_wdata

csr_rdata

csr_rdata_valid

Local_rdata_error interface

Local_rdata_error

Conduit

Indicates read data error when Error Detection and Correction logic is enabled.

Hard Memory Controller MPFE FIFO Clock Interface

mp_cmd_clk

Conduit

When you enable the Hard Memory Interface, three FIFO buffers (command, read data, and write data) are created in the MPFE. Each FIFO buffer has its own clock and reset port.

This interface is enabled when you turn on the Enable Hard Memory Interface.

mp_rfifo_clk

mp_wfifo_clk

mp_cmd_reset_n

mp_rfifo_reset_n

mp_wfifo_reset_n

Hard Memory Controller Bonding Interface

bonding_in_1

Conduit

Bonding interface to bond two controllers to expand the bandwidth. This interface is enabled when you turn on the Export bonding interface.

bonding_in_2

bonding_in_3

bonding_out_1

bonding_out_2

bonding_out_3

Did you find the information on this page useful?

Characters remaining:

Feedback Message