External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

7.3.3.5. Memory Timing Parameters for DDR2, DDR3, and LPDDR2 SDRAM for UniPHY IP

The following table lists the memory timing parameters for DDR2, DDR3, and LPDDR2 SDRAM.

Use the Memory Timing tab to apply the memory timings from your memory manufacturer’s data sheet.

Table 72.  Parameter Description
Parameter Protocol Description

tIS (base)

DDR2, DDR3, LPDDR2

Address and control setup to CK clock rise. Set according to the memory speed grade and refer to the memory vendor data sheet.

tIH (base)

DDR2, DDR3, LPDDR2

Address and control hold after CK clock rise. Set according to the memory speed grade and refer to the memory vendor data sheet.

tDS (base)

DDR2, DDR3, LPDDR2

Data setup to clock (DQS) rise. Set according to the memory speed grade and refer to the memory vendor data sheet.

tDH (base)

DDR2, DDR3, LPDDR2

Data hold after clock (DQS) rise. Set according to the memory speed grade and refer to the memory vendor data sheet.

tDQSQ

DDR2, DDR3, LPDDR2

DQS, DQS# to DQ skew, per access. Set according to the memory speed grade and refer to the memory vendor data sheet.

tQHS

DDR2, LPDDR2

DQ output hold time from DQS, DQS# (absolute time value)

tQH

DDR3

DQ output hold time from DQS, DQS# (percentage of tCK). Set according to the memory speed grade and refer to the memory vendor data sheet.

tDQSCK

DDR2, DDR3, LPDDR2

DQS output access time from CK/CK#. Set according to the memory speed grade and refer to the memory vendor data sheet.

tDQSCK Delta Short

LPDDR2

Absolute difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts in a 160ns rolling window. Set according to the memory speed grade and refer to the memory vendor data sheet.

tDQSCK Delta Medium

LPDDR2

Absolute difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts in a 1.6us rolling window. Set according to the memory speed grade and refer to the memory vendor data sheet.

tDQSCK Delta Long

LPDDR2

Absolute difference between any two tDQSCK measurements (within a byte lane) within a contiguous sequence of bursts in a 32ms rolling window. Set according to the memory speed grade and refer to the memory vendor data sheet.

tDQSS

DDR2, DDR3, LPDDR2

First latching edge of DQS to associated clock edge (percentage of tCK). Set according to the memory speed grade and refer to the memory vendor data sheet.

tDQSH

DDR2, LPDDR2

DQS Differential High Pulse Width (percentage of tCK). Specifies the minimum high time of the DQS signal received by the memory. Set according to the memory speed grade and refer to the memory vendor data sheet.

tQSH

DDR3

tDSH

DDR2, DDR3, LPDDR2

DQS falling edge hold time from CK (percentage of tCK). Set according to the memory speed grade and refer to the memory vendor data sheet.

tDSS

DDR2, DDR3, LPDDR2

DQS falling edge to CK setup time (percentage of tCK). Set according to the memory speed grade and refer to the memory vendor data sheet.

tINIT

DDR2, DDR3, LPDDR2

Memory initialization time at power-up. Set according to the memory speed grade and refer to the memory vendor data sheet.

tMRD

DDR2, DDR3

Load mode register command period. Set according to the memory speed grade and refer to the memory vendor data sheet.

tMRW

LPDDR2

tRAS

DDR2, DDR3, LPDDR2

Active to precharge time. Set according to the memory speed grade and refer to the memory vendor data sheet.

tRCD

DDR2, DDR3, LPDDR2

Active to read or write time. Set according to the memory speed grade and refer to the memory vendor data sheet.

tRP

DDR2, DDR3, LPDDR2

Precharge command period. Set according to the memory speed grade and refer to the memory vendor data sheet.

tREFI

DDR2, DDR3

Refresh command interval. (All banks only for LPDDR2.) Set according to the memory speed grade and temperature range. Refer to the memory vendor data sheet.

tREFICab

LPDDR2

tRFC

DDR2, DDR3

Auto-refresh command interval. (All banks only for LPDDR2.) Set according to the memory device capacity. Refer to the memory vendor data sheet.

tRFCab

LPDDR2

tWR

DDR2, DDR3, LPDDR2

Write recovery time. Set according to the memory speed grade and refer to the memory vendor data sheet.

tWTR

DDR2, DDR3, LPDDR2

Write to read period. Set according to the memory speed grade and memory clock frequency. Refer to the memory vendor data sheet. Calculate the value based on the memory clock frequency.

tFAW

DDR2, DDR3, LPDDR2

Four active window time. Set according to the memory speed grade and page size. Refer to the memory vendor data sheet.

tRRD

DDR2, DDR3, LPDDR2

RAS to RAS delay time. Set according to the memory speed grade, page size and memory clock frequency. Refer to the memory vendor data sheet. Calculate the value based on the memory interface frequency and memory clock frequency.

tRTP

DDR2, DDR3, LPDDR2

Read to precharge time. Set according to memory speed grade. Refer to the memory vendor data sheet. Calculate the value based on the memory interface frequency and memory clock frequency.

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