External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

1.1.6. QDR II and QDR II+ SRAM Clock Signals

QDR II and QDR II+ SRAM devices have two pairs of clocks, listed below.

  • Input clocks K and K#
  • Echo clocks CQ and CQ#

In addition, QDR II devices have a third pair of input clocks, C and C#.

The positive input clock, K, is the logical complement of the negative input clock, K#. Similarly, C and CQ are complements of C# and CQ#, respectively. With these complementary clocks, the rising edges of each clock leg latch the DDR data.

The QDR II SRAM devices use the K and K# clocks for write access and the C and C# clocks for read accesses only when interfacing more than one QDR II SRAM device. Because the number of loads that the K and K# clocks drive affects the switching times of these outputs when a controller drives a single QDR II SRAM device, C and C# are unnecessary. This is because the propagation delays from the controller to the QDR II SRAM device and back are the same. Therefore, to reduce the number of loads on the clock traces, QDR II SRAM devices have a single-clock mode, and the K and K# clocks are used for both reads and writes. In this mode, the C and C# clocks are tied to the supply voltage (VDD). Intel® FPGA external memory IP supports only single-clock mode.

For QDR II or QDR II+ SRAM devices, the rising edge of K is used to capture synchronous inputs to the device and to drive out data through Q[x:0], in similar fashion to QDR II SRAM devices in single clock mode. All accesses are initiated on the rising edge of K .

CQ and CQ# are the source-synchronous output clocks from the QDR II or QDR II+ SRAM device that accompanies the read data.

The Intel® device outputs the K and K# clocks, data, address, and command lines to the QDR II or QDR II+ SRAM device. For the controller to operate properly, the write data (D), address (A), and control signal trace lengths (and therefore the propagation times) should be equal to the K and K# clock trace lengths.

You can generate K and K# clocks using any of the PLL registers via the DDR registers. Because of strict skew requirements between K and K# signals, use adjacent pins to generate the clock pair. The propagation delays for K and K# from the FPGA to the QDR II or QDR II+ SRAM device are equal to the delays on the data and address (D, A) signals. Therefore, the signal skew effect on the write and read request operations is minimized by using identical DDR output circuits to generate clock and data inputs to the memory.