External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

2.6.3. How to Enter Calculated Channel Signal Integrity Values

You should enter calculated channel loss values in the Channel Signal Integrity section of the Board (or Board Timing) tab of the parameter editor.

Arria V, Cyclone V, and Stratix V

For 28nm families, fixed values are assigned to different signals within the timing analysis algorithms of the Quartus Prime software. The following table shows the values for different signal groups:

Signal Group Assumed Channel Loss
Address/Command (output) 250 ps
Write (output) 350 ps
Read Capture (input) 225 ps

If your calculated values are higher than the assumed channel loss, you must enter the positive difference; if your calculated values are lower than the assumed channel loss, you must enter the negative difference. For example, if the measured channel loss for reads for your system is 250 ps then you should enter 25 ps as the read channel loss.

Arria 10 and Stratix 10

For Arria 10 and Stratix 10 EMIF IP, the default channel loss displayed in the parameter editor is based on the selected configuration (different values for single rank versus dual rank), and on internal Intel reference boards. You should replace the default value with the value that you calculate.

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