External Memory Interface Handbook Volume 2: Design Guidelines: For UniPHY-based Device Families

ID 683385
Date 3/06/2023
Document Table of Contents

6. QDR II/II+ SRAM Board Design Guidelines

The following topics provide guidelines for you to improve your system's signal integrity and layout guidelines to help successfully implement a QDR II or QDR II+ SRAM interface in your system.

The QDR II and QDR II+ SRAM Controller with UniPHY Intel FPGA IP enables you to implement QDR II and QDR II+ interfaces with Arria® II GX, Arria V, Stratix® III, Stratix IV, and Stratix V devices.

Note: In the following topics, QDR II SRAM refers to both QDR II and QDR II+ SRAM unless stated otherwise.

The following topics focus on the following key factors that affect signal integrity:

  • I/O standards
  • QDR II SRAM configurations
  • Signal terminations
  • Printed circuit board (PCB) layout guidelines

I/O Standards

QDR II SRAM interface signals use one of the following JEDEC I/O signalling standards:

  • HSTL-15—provides the advantages of lower power and lower emissions.
  • HSTL-18—provides increased noise immunity with slightly greater output voltage swings.

To select the most appropriate standard for your interface, refer to the Arria II GX Devices Data Sheet: Electrical Characteristics chapter in the Arria II Device Handbook, Stratix III Device Datasheet: DC and Switching Characteristics chapter in the Stratix III Device Handbook, or the Stratix IV Device Datasheet DC and Switching Characteristics chapter in the Stratix IV Device Handbook.

The QDR II SRAM Controller with UniPHY Intel FPGA IP defaults to HSTL 1.5 V Class I outputs and HSTL 1.5 V inputs.