External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.10.3. Read Data Assumptions

To verify that the external memory interface can use the FPGA Sampling Window (SW) input timing specifications, the following assumptions are necessary:
  • The read clocks input pins must be placed on DQS pins. DQS/DQS# inputs must be placed on differential DQS/DQSn pins on the FPGA.
  • Read data pins (DQ) must be placed on the DQ pins related to the selected DQS pins.
  • For QDR II and QDR II+ SRAM interfaces, the complementary read clocks must have a single‑ended I/O standard setting of HSTL‑18 Class I or HSTL‑15 Class I.
  • For RLDRAM II interfaces, the differential read clocks must have a single ended I/O standard setting of HSTL 18 Class I or HSTL 15 Class I.

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