External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

9.10.2. Write Data Assumptions

To verify the memory interface using the FPGA TCCS output timing specifications, the following assumptions are necessary:
  • For QDRII and QDRII+ memory interfaces, the write clock output pins (such as K/K# or DK/DK#) must be placed in DQS/DQSn pin pairs.
  • The PLL clock used to generate the write‑clock signals and the PLL clock used to generate the write‑data signals must come from the same PLL.
  • The slew rate for all write clocks and write data pins must be set to Fast or OCT must be used.
  • When auto deskew is not enabled, the output delay chains and output enable delay chains must all be set to the default values applied by the Quartus Prime software. These delay chains include the Stratix III D5 and D6 delay chains.
  • The output open drain for all write clocks and write data pins’ IO_OBUF atom must be set to Off. The Output Open Drain logic option must not be enabled.
  • The weak pull-up for all write clocks and write data pins must be set to Off. The Weak Pull Up Resistor logic option must not be enabled.
  • The Bus Hold for all write clocks and write data pins must be set to Off. The Enable Bus Hold Circuitry logic option must not be enabled.

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