External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

5.3.1. Input to the FPGA from the RLDRAM Components

The RLDRAM II or RLDRAM 3 component drives the following input signals into the FPGA:
  • Read data (DQ on the bidirectional data signals for CIO RLDRAM II and CIO RLDRAM 3).
  • Read clocks (QK/QK#).

Intel recommends that you use the FPGA parallel OCT to terminate the data on reads and read clocks.

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