External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.4.3.2. Interfacing with ×18 RLDRAM II and RLDRAM 3 CIO Devices

This topic describes interfacing with x18 RLDRAM II and RLDRAM 3 devices.

RLDRAM II devices have the following pins:

  • 4 pins for QK/QK# signals
  • 18 DQ pins (in ×8/×9 DQS group)
  • 2 pins for DK/DK# signals
  • 1 DM pin
  • 25 pins total (26 if you have a QVLD)

In the FPGA, you use two ×8/×9 DQS group totaling 24 pins: 4 for the read clocks and 18 for the read data.

Each ×8/×9 group has one DQ pin left over that can either use QVLD or DM, so one ×8/×9 group has the DM pin associated with that group and one ×8/×9 group has the QVLD pin associated with that group.

RLDRAM 3 devices have the following pins:

  • 4 pins for QK/QK# signals
  • 18 DQ pins (in ×8/×9 DQS group)
  • 4 pins for DK/DK# signals
  • 2 DM pins
  • 28 pins total (29 if you have a QVLD)

In the FPGA, you use two ×8/×9 DQS group totaling 24 pins: 4 for the read clocks and 18 for the read data.

Each ×8/×9 group has one DQ pin left over that can either use QVLD or DM, so one ×8/×9 group has the DM pin associated with that group and one ×8/×9 group has the QVLD pin associated with that group.

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