External Memory Interface Handbook Volume 2: Design Guidelines

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ID 683385
Date 5/08/2017
Public
Document Table of Contents

1.1.19.6. Maximum Number of LPDDR2 SDRAM Interfaces Supported per FPGA

The following table lists the maximum number of x8 LPDDR2 SDRAM components that can fit in the smallest and largest devices and pin packages, assuming the device is blank.

Each interface of size n, where n is a multiple of 8, consists of:

  • n DQ pins (including ECC)
  • n/8 DM pins
  • n/8 DQS, DQSn pin pairs
  • 10 address pins
  • 2 command pins (CKE and CSn)
  • 1 CK, CK# pin pair up to every three x8 LPDDR2 components
Table 10.  Maximum Number of LPDDR2 SDRAM Interfaces Supported per FPGA 

Device

Device Type

Package Pin Count

Maximum Number of LPDDR2 SDRAM Interfaces

Arria V

5AGXB1

5AGXB3

5AGXB5

5AGXB7

5AGTD3

5AGTD7

1,517

  • One ×72 interface on both top and bottom sides
  • No DQ pins on the left and right sides

5AGXA1

5AGXA3

672

  • One ×64 interface or two ×24 interfaces on both top and bottom sides
  • One ×32 interface on the right side

5AGXA5

5AGXA7

672

  • One ×64 interface or two ×24 interfaces on both the top and bottom sides
  • No DQ pins on the left side

Cyclone V

5CGTD9

5CEA9

5CGXC9

1,152

  • One ×72 interface or two ×32 interfaces on each of the top, bottom, and right sides
  • No DQ pins on the left side

5CEA7

5CGTD7

5CGXC7

484

  • One ×48 interface or two ×16 interfaces on both the top and bottom sides
  • One ×8 interface on the right side
  • No DQ pins on the left side

MAX 10 FPGA

10M50D672

10M40D672

762

One x16 interface on the right side

10M50D256

10M40D256

10M25D256

10M16D256

256

One x16 interface on the right side

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