External Memory Interfaces IP - Support Center

Welcome to the External Memory Interface (EMIF) support page! Here you will find information regarding Intel® Agilex®, Intel Stratix® 10, Intel Arria® 10, and Intel Cyclone® 10 FPGAs on how to plan, design, implement, and verify your external memory interfaces. You will also find debug, training, and other resource materials on this page.

This page is set up to walk you through the design process from start to finish.

For support resources regarding other FPGAs, search within the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

What's New

Intel® Agilex® FPGA EMIF IP Overview

Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cylcone® 10 EMIF IP User Guides (formerly EMIF Handbook Volumes 1 to 3)

Intel® Stratix® 10, Intel Arria® 10, and Intel® Cylcone® 10 EMIF IP Design Example User Guides

Intel® Stratix® 10 MX HBM2 IP User Guide

EMIF Device Selector now supports all Intel® Stratix® 10 devices

How Do I Select a Device?

Two tools are available to help you select an Intel® FPGA based on your memory requirements:

	EMIF Device Selector	EMIF Spec Estimator
Features	Determines memory interfaces needed to achieve a desired bandwidth Calculates bandwidth based on selected memory configurations Displays all Intel® Agilex® , Intel® Stratix® 10, and Intel® Arria® 10 FPGAs supporting selected memory interfaces	Determines required Intel® FPGA device family and speed grade needed to achieve desired performance Displays maximum frequency and DQ width available based on memory selections
Device Support	Intel® Agilex® FPGAs Intel® Stratix® 10 FPGAs Intel® Arria® 10 FPGAs	All Intel® FPGAs
Resources	Download EMIF Device Selector View EMIF Device Selector Video	Launch EMIF Spec Estimator View EMIF Spec Estimator Video

How Do I Select an External Memory Intellectual Property (IP)?

To learn about the various memory IP available, refer to the following online training curriculum:

Training Course	Description
Introduction to Memory Interfaces IP in Intel® Stratix® 10 and Arria® 10 Devices	This course covers the different external memory interface options available, as well as the architectural and hard memory controller features for Intel Stratix® 10 and Arria® 10 FPGAs
Introduction and Architecture Overview for High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices	This course covers the benefits of integrating High Bandwidth Memory into the Stratix® 10 MX FPGA devices, features and options for the hardened HBM controller, and how to generate the HBM2 IP
Controller Features for High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices	This course covers the features and options for the hardened HBM controller, and the Arm AMBA 4 AXI interface between the controller and user logic
SoC Hardware Overview	This course covers the features of the Hard Processor Subsystem (HPS) SDRAM and the AMBA AXI bridge architecture
Introduction to Hybrid Memory Cubes	This course covers the features of Hybrid Memory Cube (HMC) and its architecture

Timing Check

Note

In order to verify your design will achieve system-level timing closure, you should compile your EMIF design and make sure that the generated report does not contain any failures. Specifically, you need to verify that there are no failures in the Report DDR Timing analysis.

EMIF Timing Closure Guidelines

The EMIF Timing Closure Guidelines contains details on EMIF timing paths and the DDR Timing Report used to verify system-level timing closure.

Download Arria 10 Timing Closure Guidelines

Where Do I Find Information on the EMIF IP?

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following External Memory Interfaces IP User Guides:

How Do I Generate the EMIF IP?

For detailed information regarding External Memory Interface (EMIF) Intellectual Property (IP) parameters, refer to the following protocol-specific sections within the following EMIF IP User Guides:

	Intel® Stratix® 10	Intel® Arria® 10	Intel® Cyclone® 10
EMIF IP Parameter Descriptions	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3 HBM2	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3

For step-by-step instructions on how to generate the EMIF IP and how to create a reference design example, refer to the appropriate External Memory Interfaces IP Design Example User Guide and videos:

^{Note: The video is applicable to Intel® Stratix® 10 devices as well.}

For step-by-step instructions on how to integrate multiple EMIF IP cores into a single Platform Designer (formerly Qsys) system, refer to the following guide and video:

^{Note: The design guide is applicable to Intel® Stratix® 10 devices as well.}

For information on how to implement the various memory IP available, refer to the following online training curriculum:

Training Course	Description
Implementing High Bandwidth Memory (HBM2) Interfaces in Intel® Stratix® 10 MX Devices	This course covers how to generate and implement a FPGA design that can access HBM2
Implementing the Hybrid Memory Cube Controller IP in Intel® Arria® 10 Devices	This course covers how to generate and implement a FPGA design that can access the Hybrid Memory Cube device

How Do I Perform Functional Simulation?

For detailed information on simulating the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following section within the EMIF IP User Guides:

For instructions on how to generate an EMIF simulation design example and how to run simulations using the ModelSim*-Intel^® FPGA simulation software, refer to the following sections within the EMIF IP Design Example User Guides:

For information on how to verify an EMIF design, refer to the following online training curriculum:

Training Course	Description
Verifying Memory Interfaces IP in Arria® 10 Devices	This course covers how to verify functional of an EMIF design through simulation and how to perform timing analysis

Where Do I Find Information on FPGA Resource and Pin Placement?

For detailed External Memory Interface (EMIF) pin information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

	Intel® Stratix® 10	Intel® Arria® 10	Intel® Cyclone® 10
EMIF Pin and Resource Planning	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3

For simplified I/O placement refer to the Interface Planner for an easy-to-use drag-and-drop tool available in the Intel® Quartus® Prime Pro Edition software for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. Refer to the following videos for information on how to use the Interface Planner and its benefits:

For more information on Interface Planner for resource location assignments, refer to the following online training curriculum:

Training Course	Description
Fast & Easy I/O System Design with Interface Planner	This course covers how to implement a design resource floorplan using Interface Planner

Additional Resources

What is Ping Pong PHY?

Ping Pong PHY allows two memory interfaces to share Address and Command buses. This is supported for DDR3 and DDR4 protocols and for Stratix® V, Intel® Arria® 10, and Intel® Stratix® 10 FPGAs. Refer to the following video for information on the concept of Ping Pong PHY, its benefits, and an analysis of simulation results:

DDR4 Ping Pong PHY Video

How Do I Generate the HPS EMIF IP?

For a quick reference guide on Hard Processor Subsystem (HPS) External Memory Interface (EMIF) limitations, Intellectual Property (IP) generation, and pin constraints, refer to the following guidelines:

Intel® Arria® 10 Device HPS EMIF Guidelines

Where Do I Find Information on PHYLite?

The PHYLite IP allows you to build custom memory interface PHY blocks for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. For detailed information about the PHYLite IP, refer to the following user guide:

PHYLite for Parallel Interfaces IP Core User Guide

For detailed information on how to properly assign pinouts for PHYLite based on different DQ/DQS group sizes, refer to the following video:

PHYLite Group Pin Placement Video

^{Note: The video is applicable to Intel® Stratix® 10 devices as well.}

The PHYLite IP supports many different I/O standards and termination values on input and output buffers for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. Refer to the following video for infroamtion on how to create an On-Chip-Termination (OCT) block and how to associate it with the terminated I/O buffer in the PHYLite IP:

OCT Block for PHYLite Video

Where Do I Find Information on Board Layout and Design?

For detailed External Memory Interface (EMIF) board layout and design information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

	Intel® Stratix® 10	Intel® Arria® 10	Intel® Cyclone® 10
EMIF Board Design Guidelines	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3

How Do I Perform Board/Channel Simulation?

For information on measuring write-and-read Intersymbol Interference (ISI) and Crosstalk, arranging Command, Address, Control and Data pins, and I/O bank placement restrictions, refer to the following guidelines:

^{Note: The Intel® Arria® 10 channel guidelines is applicable to Intel® Stratix® 10 devices as well.}

How Do I Calculate Board Skew and Channel Loss?

Two tools are available to help you calculate board skew and channel loss:

	Board Skew Parameter Tool	Channel Loss Calculation Tool
Features	Calculates board skew due to PCB traces and multi-rank designs	Calculates channel loss due to Intersymbol Interference (ISI) and Crosstalk on Command, Address, Control, and Data signals
Support	All Intel® FPGAs All memory protocols	Intel® Arria® 10 and Intel® Stratix® 10 FPGAs DDR memory protocols Compatible with Mentor Graphics HyperLynx Signal Integrity software only
Resources	Download Board Skew Parameter Tool View Board Skew Parameter Tool Video	Download Channel Loss Tool

Where Do I Find Information on Timing Closure?

For information regarding External Memory Interface (EMIF) timing closure, refer to the following section within the EMIF Intellectual Property (IP) User Guides:

How Do I Debug My External Memory Interface Design?

For information regarding debugging the external memory interface (EMIF) intellectual property (IP), refer to the following section within the EMIF IP User Guides:

The main tool available for debug is the EMIF Debug Toolkit:

	EMIF Debug Toolkit
Features	Displays pre and post calibration margins per DQS group and DQ pin Generates read/write eye diagrams per DQ pin (2-D eye diagram) Allows customizable real-time traffic generator for test/debug (Traffic Generator 2.0) Captures read/write margins during user-mode traffic (Driver Margining)
Support	Compatible with EMIF design example projects and custom EMIF designs containing one or more memory interfaces Supports all memory protocols
Accessibility	Accessible through the Intel® Quartus® Prime software (Tools > System Debugging Tools > External Memory Interface Toolkit)

How Do I Use the EMIF Debug Toolkit?

For step-by-step instructions on how to daisy-chain multiple memory interfaces for compatibility with the EMIF Debug Toolkit, refer to the following user guide:

Debugging Multiple Memory Interfaces Guide

The Read/Write 2-D Eye Diagram feature available in the EMIF Debug Toolkit generates read-and-write eye diagrams for each data pin. Refer to the following video for information on important voltage reference parameters during the EMIF IP generation process and how to use the 2-D Eye Diagram feature:

2-D Eye Diagram Video

The Traffic Generator 2.0 allows you to test and debug your external memory interface through customizable traffic and test patterns. Refer to the following guide and videos for detailed information on how to use the Traffic Generator 2.0 feature:

The Driver Margining feature allows you to capture read-and-write margining data per pin during user-mode traffic. Refer to the following videos for information on the differences between driver margining and calibration margining, and instructions on how to use the Driver Margining feature:

For information on how to debug an EMIF design, refer to the following online training curriculum:

Training Course	Description
On-Chip Debugging of Memory Interfaces IP in Arria® 10 Devices	This course covers how to perform debug using the EMIF Toolkit or On-Chip Debug Toolkit, how to use Traffic Generator 2.0, and configure multiple memeory interface designs for compatibility with these debug tools

Where Can I Find Information Regarding Optimizing Controller Performance?

For information regarding controller performance and efficiency, refer to the following section within the External Memory Interfaces (EMIF) Intellectual Property (IP) User Guides:

How Do I Learn About Known Issues Regarding EMIF?

For information on supported features for the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following release notes:

Intel® Arria® 10 Device External Memory Interface IP Core Release Notes
Intel® Stratix® 10 Device External Memory Interface IP Core Release Notes - coming soon

For information on current and known issues regarding the EMIF IP, refer to the Knowledge Base:

Title
Error nofile(37) in protected region
How do I download the latest version of the Board Skew Parameter Tool?
How do I decide when to compensate for the package delay mismatch (Package Deskew) when routing the board traces for my memory interface?
Intel® Stratix® 10 SX Device Features
Package effects when probing at the FPGA pin
Does Altera provide support for Multi-port Front End IP implemented in the core FPGA fabric?
Is there a guideline and checklist for debugging calibration failure
ERR_MaxRefsPostponed :: More than a total of 8 Refresh commands postponed by more then trefi = &lt;trefi_value&gt; ns
Critical Warning: PLL clock *\|divclk not driven by a dedicated clock pin or neighboring PLL source.
Critical Warning: PLL clock *\|divclk not driven by a dedicated clock pin or neighboring PLL source.
How do I implement the half rate bridge option for connection to a full rate memory controller ?
Does the UniPHY External Memory Interface IP support dynamic reconfiguration of it's parameters ?
What are the minimum memory clock frequencies supported by the UniPHY External Memory Interface IP ?
What is the afi_reset_export_n port used for?
Why do I see long simulation times when simulating UniPHY-based controllers in skip calibration mode?
Internal Error: /JTAG/serial_flash_loader_0 () does not have a matching existing connection path
Why is tREFI value in simulation and board measurement different from what is set in Altmemphy and UniPHY based DDR2 SDRAM memory controller?
Error (129036): Output port DATAOUT on atom "&lt;slave DQS signal&gt;", which is a arriav_delay_chain primitive, is not connected to a valid destination
Why does the example design simulation fail when the UniPHY controller is generated with PHY only option?
The supplied JTAG Debug Information (.jdi) file for the project does not appear to match the specified target device as not all nodes have hierarchy info.
Error: Error during execution of script generate_ed.tcl: &lt;example design&gt;: Interface seq_debug tried to export unknown interface if0.seq_debug
Can the DDR3 mem_reset_n signal be controlled by a user-accessible register?
Warning (15946): DQS_INPUT_FREQUENCY parameter of DQS delay chain should be equal to the INPUT_FREQUENCY parameter of DLL
WARNING: altera_mem_if_sequencer_cpu_no_ifdef_params_sim_cpu_inst_test_bench/av_ld_data_aligned_unfiltered is ‘x’
Critical Warning: _p0_pin_map.tcl: Failed to find PLL clock for pins
Internal Error: io_obuf_iterm->is_inverted() == comp_obuf_iterm->is_inverted()
* Error: Module parameter 'CFG_CMD_GEN_OUTPUT_REG' not found for override at alt_mem_ddrx_controller.v
** Warning nofile(37) in protected region.
Can the address pins be swapped on my DDR2 or DDR3 UniPHY controller?
How do I set the timing parameters for DDR3L?
Why does the EMIF toolkit generate a blank report when masking a rank?
Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of &lt;block ID number&gt; (&lt;number of pins&gt; locations affected)
What are the AC voltage levels that Quartus® II uses for UniPHY DDR3 and DDR3L tDS and tIS set up derating ?
How do I reduce the UniPHY DDR3 controller pulsing avl_ready low on the Avalon interface?
Why do I see bit errors with my DDR3 controller?
Why do I see R105 warnings on the DDR3 reset paths when using the Design Assistant tool?
Why does the example design for the UniPHY-based memory controller have an Avalon-MM slave port as top-level I/O?
What are the local_cal_success and local_cal_fail signals of UniPHY-based memory controllers?
ncelab: *E,USMSLC (../submodules/sequencer_scc_mgr.sv,321\|24): Unsupported memory slice specification using part select or indexed part select.
Is there a way to control the latency between afi_rdata_en and afi_rdata_valid in the UniPHY-based memory controllers?
How do you export the EMIF Toolkit full calibration and margin report in one file ?
Error: Error during execution of "{C:/altera/12.1/quartus//../nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
WARNING: Attempting to read from uninitialized location
Why is my HPS DDR3 controller failing calibration?
Why do I get a no-fit when using the Altera External Memory Interface IP in an FPGA device that has a relatively low number of IO banks?
Why does the Avalon interface of my DDR3 UniPHY-based memory controller use Avalon-MM signals instead of Avalon-ST signals?
Do the UniPHY-based memory controllers support Short ZQ Calibration?
Why does my project with a RLDRAM or QDR interface stall in the fitter?
What are the AC voltage levels that Quartus® II uses for DDR2 and LPDDR2 tDS and tIS set up derating ?
Why does the EMIF toolkit fail to recognize the memory interface when it is generated in Qsys?
Error: Could not find a location with: OCT_CAL_BLOCK_ID
Why is afi_rlat tied to ground in my UniPHY-based PHY-Only instance of the external memory interface?
Why is my Qsys UniPHY based memory controller missing the pin_assignments.tcl file and other support files?
Error : Illegal constraint of DLL to the region (X, Y) to (X, Y): no valid locations in region
How do I calculate the ECC for DDR3 UniPHY based controller?
Why are the DDR3 controller write-to-read and read-write turnaround times longer than expected?
How do I remove the on-chip termination from my UniPHY-based memory controller?
Why is tRCD larger than expected with my DDR3 UniPHY controller?
Error: s0: Error during execution of "<Intel® Quartus Prime installation>/nios2eds/Nios II Command Shell.bat} make all 2>> stderr.txt": child process exited abnormally
Warning (332009): The launch and latch times for the relationship between source clock: and destination clock: are outside of the legal time range. The relationship difference is correct, however the launch time is set to 0.
Error (15700): Termination calibration block atom "&lt;variation name&gt;\|altera_mem_if_oct_stratixv:oct0\|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout
Why do I observe read errors with my UniPHY based memory controller IP after migrating the IP to a different version of the Quartus II software?
Error: Channel uncertainties must be greater than or equal to 0
Could not find the TCP port for the System Console process within the elapsed time limit
Where can I find the ALTMEMPHY and UniPHY IP tutorials and example design projects that were previously covered in the External Memory Interface Handbook?
Why has the option "Enable read DQS tracking" in UniPHY based DDR3 SDRAM IP changed between Quartus II software releases?
Is it possible to retain data in a memory device during the UniPHY calibration process?
How config_data is shifted into the scan chain block when dynamic reconfiguration is used in ALTDQ_DQS2 Megafunction?
Why do the CSR registers report ECC data errors when the read data is not corrupted?
Error (175006): Could not find path between source global or regional clock driver and the HMC
Why do I see random read errors when using the DDR2, DDR3/DDR3L and LPDDR2 UniPHY IP on the Arria V GX/GT/SX/ST and Cyclone V E/GX/GT/SE/SX/ST devices?
Error: "933.333" is not a valid memory speed grade
Why is avl_ready stuck low in my DDR3 UniPHY-based controller in Quartus II 12.0SP2?
How do I fix the core setup timing violations when I bond two DDR3 hard memory controllers from the top edge to bottom edge of the FPGA device?
Why is the afi_half_clk signal not constrained in my UniPHY-based memory controller?
Can I implement single rank DDR2 SDRAM or DDR3 SDRAM DIMM/device for a design created for dual rank?
Is table below in Arria V and Cyclone V handbook DQ/DQS number for hard memory controller?
Why do I see random read errors using DDR2 SDRAM Controller with UniPHY/ DDR3 SDRAM Controller with UniPHY or LPDDR2 SDRAM Controller with UniPHY?
Does <instance_name>_pin_assignment.tcl script for DDR, DDR2 and DDR3 SDRAM High Performance controller I and II automatically find the memory pin name at top level design?
Are there any issues with the UniPHY IP Global Signal assignments seen in the Quartus II software Assignments editor after running the <variation_name>_pin_assignments.tcl script?
Why is the DDR3 HMC with multiple MPFE ports hanging in simulation with ModelSim
Why does the DDR3 hard memory controller with UniPHY return invalid read data after the individual multi-port front end port is reset?
Can the PCIe Hard IP core and the DDR3 IP core share the same refclk?
Why is the EMIF debug toolkit hanging in 12.0SP2?
How do I connect the signals of the ALTDQ_DQS2 Hard Read FIFO?
Should I use the option "Generate power-of-2 data bus widths for Qsys or SOPC Builder" in DDR2 or DDR3 SDRAM Controller with UniPHY?
Critical Warning (10169): Verilog HDL warning at alt_mem_ddrx_controller.v(495): the port and data declarations for array port "afi_rrank" & "afi_wrank" do not specify the same range for each dimension
Can I generate a hard memory controller without the hard MPFE?
Why do I see incorrect read data when using a Hard Memory Controller with multiple MPFE ports?
Why the Maximum Avalon-MM burst length options in DDR2/DDR3 SDRAM UniPHY based Controller does not match with the other Qsys component like Maximum burst size (words) in Avalon-MM Pipeline Bridge?
Is there a way to choose which rank to be calibrated first in multiple rank DDR3 SODIMM design?
Why is the efficiency of the Cyclone V and Arria V hard memory controller lower than expected for single port designs?
Warning (332174): Ignored filter at &lt;variation name&gt;_p0.sdc(679): _UNDEFINED_PIN__driver_core_clk could not be matched with a clock
Why does the external memory interface calibration hang after a CvP update when using the DDR3, DDR2 or LPDDR2 UniPHY hard memory controller?
Can I share a single PLL for two ALTMEMPHY instances in my design?
Error (12002): Port "strobe_n_io" does not exist in macrofunction "dq_ddio.ubidir_dq_dqs"
Which tDQSS timing parameter should be used in the UniPHY LPDDR2 IP Memory Timing tab of the parameter editor?
Error (175005): Could not find a location with: OCT_CAL_BLOCK_ID of (value)
How should I place the QDRII/QDRII+ mem_cq and mem_cq_n pins in Arria V GX/GT/ST/SX devices?
Are there any issues with the UniPHY LPDDR2 IP address and command pinout ?
Error (14024): Parameter "mem_if_tcwl" of instance "hmc_inst" has illegal value "TCWL_1" assigned to it. Possible parameter values are: "TCWL_8", "TCWL_7", "TCWL_6", "TCWL_5", "TCWL_4", "TCWL_3", "TCWL_2", "TCWL_0".
Critical Warning: _p0_pin_map.tcl: Failed to find PLL clock for pins :s0\|*:sequencer_scc_mgr_inst\|scc_state_curr.STATE_SCC_IDLE
What causes an MPFE port to lock up?
Can I swap DQ pins of the HMC to ease routing congestion?
Critical Warning (11887): The following pin &lt;data pin&gt; was placed in a reserved GND location. This may cause decreased performance for HMC. Altera recommends the pin location to be grounded
Why is my UniPHY External Memory Interface Toolkit timing out?
Critical warning: _p0_pin_map.tcl: Failed to find PLL clock for pins
Does the EMIF Toolkit Efficiency Monitor and Protocol Checker support the Arria V and Cyclone Hard Memory Controller ?
What is the value of the constantBurstBehavior property in my DDR3 SDRAM Controller with UniPHY?
Are the timing violations on the bonding interface of my Cyclone V or Arria V DDR3 bonded hard memory controller design valid?
Warning: Illegal value detected on input clock
Why is my DDR2 UniPHY controller interface only 50% efficient for back-to-back read or write commands?
Why does a delay sometime occur when accessing DDR3 memory ?
When using the UniPHY-based hard memory controller, why do I see timing violations between the ports on the MPFE block?
Does the ALTDQ_DQS2 IP support LPDDR2 memory?
Why is the UniPHY based memory controller design not meeting timing?
Why does DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM Altmemphy and UniPHY based controllers violate the maximum refresh interval specified in the memory preset editor in the controller GUI?
Warning (10230): Verilog HDL assignment warning at instance_name_write_datapath.v(118): truncated value with size to match size of target (1)
How do I connect my DDR3 controller to a 72-bit x4 DDR3 RDIMM?
Possible Timing Failure on Designs Targeting Arria V and Cyclone V Devices
ERROR: The supplied JTAG Debug Information (.jdi) file for the project does not appear to match the specified target device as not all nodes have hierarchy info.
How does the Avalon data bus map to the external DDR3 bus for DDR3 with ECC interface?
Can I instantiate a master/slave DDR3 UniPHY example design in a top-level wrapper file?
Why do I see a DQS write preamble (tWPRE) violation in hardware when using DDR3 or DDR2 SDRAM hard memory controller with UniPHY?
How do I determine the maximum frequency for DDR3 interfaces using an SODIMM?
Why does the Avalon bus lock up when simulating a DDR2 SDRAM and DDR3 SDRAM Controller with UniPHY generated in version 11.0?
Error: The parameter MEM_CS_WIDTH (Number of chip-selects per device/DIMM) must be set to 2 or greater for RDIMM/LRDIMM devices
Why does avl_ready deassert after avl_write_req is asserted in my DDR3 and DDR2 SDRAM High Performance Controller II IP?
Is there any issue with DDR, DDR2, DDR3 SDRAM High Performance controller generated testbench regarding dm_delayed signal?
Fatal Error: Read data comes back but dynamic OCT ctrl is not in read mode
Why are the Avalon byte enables not implemented in my DDR3 UniPHY controller version 11.0?
Why is CAS latency of 2 or 2.5 not supported for DDR SDRAM Altmemphy or DDR SDRAM High Performance Controller?
Why can't I place a DDR3 UniPHY-based controller in quadrant 1 or 2 in a Cyclone V or Arria V SoC device?
EMIF Maximum Frequency Specification Update for Stratix V
Possible Simulation Failure in Skip Calibration Mode
Long Term CK Jitter Exceeds Spec in HPS Memory Interface in Arria V and Cyclone V Devices
Critical Warning: BWS group of size 0
Is there any issue with selecting the option Enable Avalon-MM byte-enable signal when generating RLDRAMII Controller with UniPHY?
Why is avl_ready de-asserting after a read or write request?
Can I disable option "Enable Avalon-MM byte-enable signals" when implementing DDR3 SDRAM UniPHY based controller IP in Qsys?
What files do I need to update in my UniPHY controller when OCT sharing is enabled?
Error (15700): Termination calibration block atom "<your_instance>\|altera_mem_if_oct_stratixv:oct0\|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout
Why is ODT asserted for more than one rank in my DDR3 UniPHY controller?
Error (175020): Illegal constraint of PLL output counter to the region (X, Y) to (X, Y): no valid locations in region Error (177013): Cannot route from the PLL output counter output to destination dual-regional clock driver because the destination is in the wrong region
Error: {instance_name}: Module has too many unassociated clocks ({instance_name}.pll_ref_clk, {instance_name}.afi_half_clk_in). Only one unassociated clock is allowed
Does QDRII SRAM UniPHY based interface support or require setup and hold derating for slew-rate like DDR2 SDRAM or DDR3 SDRAM UniPHY based controller IP?
Why is the QDRII+ SRAM UniPHY based controller IP not generating QVLD signal for the interface?
Why do I see discontinuity in the read data burst on mem_dq bus even when I do not change the row address during the read operation using DDR3 SDRAM UniPHY and Altmemphy based controller?
Critical Warning: DOFF group of size 0
Is there an issue with “Skip memory initialization” option in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller?
Does UniPHY IP support unaligned reads and writes on the AFI interface?
Is there an issue with Error Correcting Code (ECC) feature in DDR3 SDRAM and DDR2 SDRAM UniPHY based controller in version 11.0?
Possible to Select Unsupported Device Family for LPDDR2 Interface
Generation Error or Simulation Failure for VHDL LPDDR2 Interface
Calibration Failure Occurs when RELEASE_CLEARS_BEFORE_TRI_STATES is On
Possible Internal Error with Arria V or Cyclone V Designs Using Hard Memory Controller
Warning: DQ I/O pins fed by DQS I/O pin assigned different I/O standards
How long does it take for the Intel® PHYLite IP output delay to take effect when performing dynamic reconfiguration?
Can the MMR interface be used in conjunction with the Efficiency Monitor in External Memory Interface Intel® FPGA IP?
Are there any known issues when trying to connect the EMI Toolkit to a design?
How do I calculate the address range supported by UniPHY DDR2 or DDR3 External Memory Interface IP ?
&lt;slave_name&gt;.ctrl_amm_avalon_slave_0 does not have byteenables. Writes from narrow master &lt;master_name&gt;.master may result in data corruption
Error (11802): Can't fit design in device.
Error (15700): Termination calibration block atom "<your_instance>\|altera_mem_if_oct_stratixv:oct0\|sd1a_0" uses RZQIN port, which must be connected to a dedicated I/O atom with no other fanout
Why do I see errors when compiling Qsys system for DDR3 UniPHY based controller with Hard Processor System (HPS)?
Rule C101: Gated clock should be implemented according to the Altera standard scheme
Rule C103: Gated clock does not feed at least a pre-defined number of clock ports to effectively save power
Rule C105: Clock signal should be a global signal
Cyclone V SoC and Arria V SoC Hard Processor System SDRAM calibration fails with the Quartus II software versions 13.1.1 and 13.1.2
Postfit Simulation of UniPHY Hard Memory Interfaces is Not Supported for Arria V Devices
LPDDR2 Timing Closure Problem with Arria V Devices
VHDL Post-Fit Simulation Failure on Stratix V Devices
Warning Messages Displayed for UniPHY External Memory Interfaces When Compiling for Stratix V Devices
QDR II and QDR II+ SRAM Controller with UniPHY IP Core May Not Operate Below 167MHz
Arria V and Cyclone V Hard Memory Controller Options May Not Function Correctly for Interfaces with 2 Chip Selects
Illegal Speed Grade Error with Arria V and Cyclone V Devices
How to manually instantiate the hard input FIFO from ALTDQ_DQS2 in Stratix V?
Error: Output port DATAOUT on atom dqs_in_delay_1 which is a arriav_delay_chain primitive, is not connected to a valid destination
Error: Could not place PHY_CLKBUF {instance_name}:{instance_name}_inst\|{instance_name}_0002: {instance_name}_inst\|{instance_name}_p0:p0\|{instance_name}_p0_controller_phy:controller_phy_inst\|{instance_name}_p0_memphy_top:memphy_top_inst\|uphy_clkbuf_memphy Error: PHY_CLKBUF location is occupied
Warning : Input frequency violation on DLL instance
How do I determine the failing calibration stage for a Cyclone V or Arria V HPS SDRAM controller?
Warning (177007): PLL(s) placed in location &ltPLL location&gt do not have a PLL clock to compensate specified - the Fitter will attempt to compensate all PLL clocks
How do you use the DQS phase-shift circuit when the memory interface frequency is below the DLL minimum reference clock frequency?
What can cause a calibration failure on the odd numbered ranks of a multiple rank DDR3 or DDR4 interface ?
What is the "minimum pulse width timing specification" of the global reset signal for the UniPHY Controller?
What is the minimum pulse width timing specification of the global reset signal in UniPHY IP?
Is there an issue with "Enable Auto Power Down" option in DDR2 and DDR3 SDRAM UniPHY based controller generated in Quartus II software version 11.0 and 11.0SP1?
How do I connect csr_debugaccess and csr_burst_count ports generated by DDR3 SDRAM Controller with UniPHY?
Internal Error: Sub-system: FSV, File: /quartus/fitter/fsv/fsv_module_mint.cpp, Line: 1869 driver_atom->is_clkbuf()
How do I view the external memory signals in my HPS SDRAM simulation?
Why do I see an efficiency issue when using the Arria V and Cyclone V hard memory controller with DQS tracking enabled?
Why is there a "reserved_mem_reserved_pins_for_dk_group" pin in RLDRAM II-UniPHY based controller in the Stratix V device?
Does UniPHY External Memory Interface debug toolkit support all the speed grades for Stratix III and Stratix IV FPGA devices?
Why assertion of reset may cause low probablity lock up of UniPHY NIOS sequencer resulting in incomplete calibration
Does Quartus II software support x36 QDRII/II+ SRAM emulation mode in Stratix V devices?
Why do I get a Fitter error when compiling LPDDR2 soft memory controller?
Do I need to make user assignments for Cyclone V hard memory controller ground pins?
Error (181011): Incompatible on-chip termination settings detected for pins in the DQS group fed by DQS I/O pin "&lt;QK clock pin&gt;". All pins in group must use the same OCT control block.
Error Messages for UniPHY External Memory Interfaces in ModelSim Flow for Eclipse
Migrating UniPHY IP from 13.0 SP1 DP5 to 13.1 Resets GUI to Default Values
ECC Not Enabled in Cyclone V SoC HPS Devices
Deep Power Down Issue With LPDDR2 Interfaces on Cyclone V Devices Using Hard Processor System
Unable to establish a connection because no memory interface targets exist on the linked device.
An error occurred while linking the project to the device
Why is my DDR3L SDRAM UniPHY based controller design missing some pin assignments?
Why does the UniPHY CORDROP_ERROR register show a non-zero value?
Error (170084): Can't route signal "\|altdq_dqs2_stratixv:altdq_dqs2_inst\|dqs_enable_int" to atom "\|altdq_dqs2_stratixv:altdq_dqs2_inst\|dqs_ff"
Why do I see a mismatch between the IBIS simulation model and the actual hardware measurement for the read DQ waveform when using the HPS external memory interface?
What is the frequency range of SDRAM output clocks in HPS?
Does Cyclone V -C8 device support DDR3 Soft Memory Controller?
Critical Warning: <corename>_if0_p0_pin_map.tcl: Failed to find PLL clock for pins if0\|p0\|controller_phy_inst\|memphy_top_inst\|afi_half_clk_reg
Are there any issues with using the UniPHY EMIF toolkit with SOPC builder projects ?
Error (129029): Input port CLK on atom "&lt;DLL instance&gt;", which is a arriav_dll primitive, is not connected to a valid source File: &lt;project path&gt;/dll.v Line: 53
Does any memory location gets written into in DDR3 SDRAM with ALTMEMPHY in calibration write levleing stage?
PHY Clock Tree Not Driven by Optimal PLL Output Counters
Example Design for Arria V with Hard Memory Interface Uses Wrong Clock
DDR3 HPS Interfaces Supported Only to 450 MHz on Arria V SoC ES Devices
Low Probability of Calibration Failure Following Repeated Resets
Simulation of ALTMEMPHY IP with Cyclone IV Devices Fails
pll_sharing Warning Message May Appear
Soft Controller May Not Meet Timing When Data Reordering is Enabled
Write Timing Violation at 550MHz for QDR II and QDR II+ SRAM Controller with UniPHY
QDR II/II+ Interfaces Targeting Arria V Devices Must Use the Nios II-Based Sequencer
x8 and x16 HPS Designs not Supported on Arria V and Cyclone V Devices
Non-leveled DDR2 Topology Fails Timing with Stratix V Devices for DDR2 and DDR3 SDRAM Controller with UniPHY
Is there any issue with Cyclone V SoC HPS support for DDR2 design which has width less than 24 bits?
Error (170084): Can't route signal "~GND" to atom "< dqs_oct_alignment~_Duplicate>"
Are there any known issues in ALTMEMPHY-based DDR2 and DDR3 SDRAM memory interface designs that could cause hardware functional failures (memory data corruption)?
Error: Can't place CQn I/O "mem_cq[0]" to a non-CQn I/O location Pin
Are the guidelines to place K and Kn pins for QDRII/+ SRAM interface when implementing the interface with UniPHY based IP different from the ones for ALTMEMPHY based IP?
When using UniPHY IP in Stratix V devices, what are the options for changing the calibrated OCT termination values from the default values ?
Why do I get timing violation associated with CK clock domain when implement multiple RLDRAM II interfaces sharing a single PLL and DLL?
Does the Advanced clock phase control adjustment in the HPS DDR3 work?
How should I connect mem_ac_parity, mem_err_out_n, and parity_error_n signals in Altmemphy based DDR3 SDRAM High Performance Controller if I do not wish to use the parity feature in DDR3 SDRAM RDIMM?
Does Stratix V QDRII/+ SDRAM Controller at full rate have timing closure issue?
Why is the "Additional CK/CK# phase" option grayed out inside the MegaWizard GUI for the Stratix V device?
What is the difference between afi_rdata_en and afi_rdata_en_full signals in UniPHY based DDR2 SDRAM and DDR3 SDRAM Controller?
Why is my Arria V QDR II and QDRII+ SRAM controller with UniPHY IP missing a CQn clock signal ?
Does the DDR3 High Performance controller II support single-rank, dual-rank, and dual-slot Registered DIMM for Stratix III and Stratix IV devices?
Why can’t I merge PLLs for two different instances of the ALTMEMPHY IP?
Why do I see timing violations and ignored clock constraint warning messages in my UniPHY-based DDR3, DDR2, QDRII/+, or RLDRAM II memory controller design?
Why do I see long refresh cycles when using DDR3 SDRAM Controller with UniPHY in Stratix V devices?
Why is the SOPC Builder system generation only successful for the first attempt but fails for the successive attempts in Quartus II software version 10.0 as well as 10.0 SP1? When it fails, the SOPC Builder hangs during the system generation at "Info: <module_name_UniPHY>: No Extra Settings:"
Why does the time interval for four active windows during RTL simulation not match the tFAW setting in the Arria 10 FPGA DDR4 IP GUI?
Why is Report DDR timing report missing when I have multiple instances of a wide external memory interface?
Can the HPS DDR3 controller local-to-memory address mapping be changed in the simulation fileset?
How do I take the package delay into account in the board skew parameters of a Stratix V DDR3 UniPHY controller GUI?
Why is my Arria 10 DDR4 design failing compilation in the fitter when I choose "Automatically select a location" for ALERT# pin placement?
Why do the External Memory Interface DQ and DQS waveforms sometimes have poor signal quality when measured at the FPGA pin on a memory read ?
Why do I get minimum period timing violation in UniPHY based DDR3 SDRAM Controller on Stratix V device?
How can I implement the DDR2 SDRAM or DDR3 SDRAM UniPHY PHY with my custom memory controller (instead of using the integrated Altera high-performance memory controller)?
How do I configure my Micron Hybrid Memory Cube (HMC) Bus Functional Model (BFM) to operate in half-width mode (8 lanes)?
Are single bit errors corrected when the <strong>Enable Error Detection and Correction Logic</strong> option is selected and the <strong>Enable Auto Error Correction</strong> option is disabled in the DDR3 SDRAM controller with UniPHY?
What tools should I use to enable my memory to interfaces with my Altera FPGA?
Are there any known issues with tCCD_S behavior in the Arria 10 FPGA DDR4 IP?
Is UniPHY based DDR2 SDRAM memory controller supported for Cyclone IV and Arria II GX FPGA devices?
What is the maximum burst length for the hard memory controller?
Why do I see timing problems reported when using derive_pll_clocks using UniPHY-based memory controllers?
Where can I find RLDRAM 3 External Memory Interface IP for Altera FPGAs?
Why do I get no result for "Report DDR" in TimeQuest for DDR3 SDRAM UniPHY based controller?
Why do I get fitter errors when compiling a Qsys DDR3 UniPHY based controller design?
Why can I assign more than a 32-bit data width to the Arria V Hard Memory Controller ?
Error:129001 Input port OFFSET on atom "\|dll_ctrl_a_wys", which is a statixv_dll_offset_ctrl primitive, is not legally connected and/or configured
Why is the memory device I am using not included in the memory preset list?
Error (129001): Input port DQSDISABLEN on atom "\|hierarchy\|dqs_delay_chain", which is a stratixv_dqs_delay_chain primitive, is not legally connected and/or configured
Why is the hard memory controller failing calibration in a Arria V ES device?
Simulation stalls when global_reset_n is toggled early in Arria 10 DDR4 PHY-Only IP simulation
When does the UniPHY DDR3 IP use an I/O standard of SSTL-15 Class II ?
Is there any known issue using the On-chip parallel termination (RT) with UniPHY IP ?
Selected input mode termination value for data bus is not valid. Please select a value of 50 ohm or higher.
What is the largest capacity DDR3 device supported by the Arria V and Cyclone V FPGA UniPHY memory IP ?
Why does the Arria 10 External Memory Interfaces IP FPGA IO Settings for Data Bus Input Mode not support lower values than 60 ohms in the Quartus Prime software version 16.1.1 for DDR4 and QDRIV protocols?
How is it determined if I/O banks are adjacent for External Memory Interface pin-outs in Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 FPGAs?
Are there any known issues with tCCD_S behavior in the Arria 10 FPGA DDR4 IP?
Does UniPHY controller write back the data to memory when double bit error happens with enable ECC option turned ON?
Can I assign DM pin to any DQ pin location in a DQS group?
Timing violation when enable 'Extra Timing Report Clock' in DDR3 UniPHY based controller
Critical Warning (181053): PLL output counters driving PHY_CLKBUF {Hierarchy_Path}:pll0\|uphy_clkbuf_memphy are not recommended for use in the memory IP PHY clock tree and timing models may not be correct.
Why am I unable to simulate the design given with External Memory Interface handbook chapter "Using High-Performance Controller II with Native Interface Design" under Altmemphy design tutorial?
Warning-[SIOB] Select index out of bounds. Following select index is out of declared bounds : [x:0]. In module instance: &lt;inst_name&gt;. In module :&lt;module_name&gt; &ltpath&gt/alt_ddrx_bank_tracking.v", 612: int_cmd_do_activate_cached[x]
Is there any known issue that can cause calibration failure on designs with full-rate QDRII/II+ SRAM and RLDRAM II UniPHY based controller created in the Quartus II software version 10.0SP1 and earlier?
How do I connect the clock and reset for an Arria 10 HPS hard memory controller when the FPGA is not programmed?
Warning (15610): No output dependent on input pin "avl_burstbegin"
Error: Output port OUTCLK of stratixv_phy_clkbuf atom "Hierarchy\|{instance_name}_p0_memphy_top:memphy_top_inst\|uphy_clkbuf_memphy" has one or more illegal fan-outs.
Why do I get two chip selects when I generate a UniPHY DDR3 registered DIMM single rank configuration?
Why do I see mem_k and mem_k_n clock pair as unconstrained output ports in TimeQuest when I implement QDRII SRAM UniPHY based controller?
Why are some pins of adjacent banks placed on different edges of the package?
Additive Latency Not Supported for HPS Hard Memory Controller in Arria V and Cyclone V SoC Devices
Why can't two center PLLs drive two different memory controllers with UniPHY at the bottom of a Stratix V device?
What is the maximum operating frequency for an external memory interface using the custom PHY?
Why do I get an error when selecting a rank of 4 with 4 chip selects for a DDR3 LRDIMM?
Why does the Arria 10 EMIF IP remain in reset during the second RTL simulation run when using the Abstract PHY ?
What is the DLL jitter specification for external memory interfaces and does the DLL jitter change depending on the frequency of operation?
Errors in Post-Fit Simulation of EMIF Interfaces on Arria V and Cyclone V Devices
The Quartus II software verion 14.1 does not include DDR3 I/O placement rules for MAX 10 devices
Does ALTMEMPHY based DDR3 SDRAM controller IP support automatic slew rate deration for a DDR3 SDRAM device with speed grade greater than or equal to 667MHz at AC175 specification?
How does TimeQuest take DQS delay chain settings changes into account when reporting timing for ALTDQ_DQS Megafunction?
Enabling slow slew rate option for EMIF Addr/Cmd and CK
Arria 10 EMIF Simulations May Failwith Certain Versions of Riviera-PRO
Are there any placement restrictions for the Intel Stratix 10 HPS EMIF IP PLL reference clock and RZQ pin?
Why is the traffic generator 2.0 option for External Memory Interfaces IP disabled in the Intel® Quartus® Prime Pro Edition version 18.0?
Warning: When the address/command signals and the memory clock signals do not use the same slew rate setting, signals using the "Slow" setting are delayed relative to signals using "Fast" setting
Why is the tRTP timing parameter box missing from the Intel® Stratix® 10 and Intel Arria® 10 EMIF IP GUIs?
How is the address map ordering of the Avalon bus to the DDR4 memory defined for the Intel® Stratix® 10 External Memory Interfaces IP ?
Why do I see the error message in the MegaWizard when I try to generate UniPHY based DDR3 SDRAM controller for Stratix V device?
Why do I see failures when implementing multiple external memory interfaces in Arria 10 devices?
Why has the UniPHY CSR interface access latency increased in 11.0 and later version of the IP compared to 10.1 version of the IP?
How do I setup my Hybrid Memory Cube Controller (HMCC) simulation to handle larger than 2GB memory size?
Why do I have to disable the DM pins generation in the DDR3 SDRAM High Performance Controller or Altmemphy IP Megawizard when implementing DDR3 SDRAM controller in x4 mode in Stratix III or Stratix IV devices?
Why does quarter rate DDR3 UniPHY based controller design show low read efficiency?
Why is a global signal assignment to <instance_name>\|s0\|rst_controller\|alt_rst_sync_uq1\|reset_out being ignored by my UniPHY-based DDR3 controller IP?
ODT signal does not toggle when ODT Rtt nominal is off and Dynamic ODT (Rtt_wr) is on
Which locations are being used during calibration in ALTMEMPHY with leveling?
Error: couldn't read file "<variation_name>_phy_ddr_timing.tcl": no such file or directory while executing "source "<variation_name>_phy_ddr_timing.tcl" (file "<sub-directory>/<variation_name>_phy_ddr_timing.sdc" line 33)
How do I resolve timing violations on the quarter rate to half rate clock transfer in my UniPHY-based DDR3 controller design?
Why do I not see DQS tracking signals when I implement UniPHY based DDR3 SDRAM Controller above 533MHz?
Info (332171): The following clock uncertainty values are less than the recommended values that would be applied by the derive_clock_uncertainty command
Why does my DDR3 Uniphy *\|pll_c2p_write_clk clock disappear from my TimeQuest reports during certain compilations?
Critical Warning (176647): DLL atom "{instance_name}\|altera_mem_if_dll_stratixiv:dll0\|dll_wys_m" dll_wys_m" is using a clock period of "value 1" ns, which is outside the valid range for its configuration mode. When the delay buffer mode is "HIGH" and the delay chain length is "8", the valid range is from "value 2" ns to "value 3" ns.
What reference plane should the DDR4 Vref bypass capacitors connect to on my PCB?
Can I have more than one DDR3 SDRAM (with leveling) memory interface located in a single IO sub-bank for Stratix IV device family?
Why are the Arria 10 DDR4 Mode Register 4 (MR4) write/read preamble bits set incorrectly?
Error: {variation_name}_p0_pin_map.tcl: Failed to find PLL reference clock
Why are some DDR4 signals unconstrained in TimeQuest?
Why are bidirectional mem_dbi_n ports created when the 'Enable DM Pins' option is selected in the Arria 10 DDR4 controller?
Does the Arria 10 external memory interface IP support DDR4 Write CRC ?
EMIF Maximum Frequency Specification Update
EMIF Generation for Arria V or Cyclone V Devices Requires Stratix V Device Database to be Installed
New Restrictions on I/O PLL Configuration Imposed in 15.1 for Arria 10 EMIF IP
Warning Message Displayed When Driving User Logic with Custom PLL in Hard Memory Interface
Possible Calibration Error for DDR2 and DDR3 Interfaces on Arria V, Cyclone V, and Stratix V Devices
Why do the DDR4 memory interface signals show values of ‘hxx in the waveforms of the example testbench simulation?
How can the Intel® Stratix®10 MX HBM2 controller efficiency be improved?
What is the flow to modify the Intel® Stratix® 10 SoC Development Kit HPS DDR4 width and ECC configuration using the Golden Hardware Reference Design project as the starting point?
Why I can not find AN435:Using DDR and DDR2 SDRAM Devices in Stratix III and Stratix IV Devices on Altera website?
Are there any Arria 10 DDR4 IP parameters that changed in the Quartus Prime software version 15.1?
Why am I seeing a difference in the option of number of chip selects for DDR3 UniPHY IP generated in Quartus II V12.0 and V13.0 and later versions?
Why is the Cyclone V SoC Device SDRAM interface Vref pin voltage incorrect ?
Why do I see an extra read data valid assertion on the Arria 10 EMIF MMR interface?
Why are some DDR4 signals unconstrained in TimeQuest?
Error (169026): Pin oct_rzqin is incompatible with I/O bank {bank}. It uses I/O standard SSTL-135, which has VCCIO requirement of 1.35V. That requirement is incompatible with bank's VCCIO setting or other output or bidirectional pins in the bank using VCCIO 2.5V.
Error: The specified Memory clock frequency exceeds the Memory device speed grade of 533.333 MHz. Please increase the Memory device speed grade (in Memory Parameters tab) or decrease the Memory clock frequency.
Is there an issue with device migration in Cyclone IV devices when implementing DDR SDRAM or DDR2 SDRAM interface with ALTMEMPHY based controller?
Can unused HPS EMIF pins be used as FPGA GPIOs?
Why do I see the error message from External Memory interface tool kit when I connect through JTAG?
Internal Error: Programmable pre-emphasis option is set to 1 for pin dut_mem_mem_par(0)~pad, but setting is not supported by I/O standard SSTL-12 with Slew Rate 0
What is the pull-up resistor guideline for the DDR4 alert_n signal?
Why do I get 3 unconstrained clocks in TimeQuest for my DDR3 controller in Arria V devices?
Can I enable Multiple controllers clock sharing in ALTMEMPHY based High Performance Memory Controller in SoPC builder for Cyclone III and IV device?
Error: Slow slew rate is not compatible with on-chip output termination for the address/command bus. Either turn off output termination (if possible), or use Fast slew rate.
Why does Quartus II Fitter automatically fit a mem_dq on preassigned DM pin on Cyclone IV device?
Warning: Ignored assignment: set_false_path -from [get_pins -compatibility_mode {_alt_mem_phy_inst\|mmc\|mimic_done_out}] -to [get_keepers {_alt_mem_phy_inst\|seq_wrapper\|seq_inst\|dgrb\|v_mmc_seq_done_1r}]
Critical Warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os
Should I use an industrial marked FPGA with my industrial temperature rated DDR SDRAM?
Error: **_emif_a10_hps_0: PLL reference clock frequency of 25.0 MHz is invalid. Please select another value, or enable the option to use the recommended value.
Why have the Arria 10 External Memory Interfaces IP Slew Rate parameters been removed in the Quartus Prime software version 15.1 ?
Error (10149): Verilog HDL Declaration error at core_debug.sv(1): identifier "seq_core_debug_pkg" is already declared in the present scope
Warning-[PCWM-W] Port connection width mismatch &ltpath_name&gt;/SdramController_PLL_Master_phy_alt_mem_phy.v, 1395"clk". The following 1-bit expression is connected to 2-bit port "scan_din" of module "SdramController_PLL_Master_phy_alt_mem_phy_clk_reset", instance "clk" Expression: scan_din[0] use +lint=PCWM for more details
Is there an issue with sharing OCT between master and slave UniPHY based controller IPs for Stratix V RLDRAMII and QDRII?
What is the default Local-to-Memory address mapping in the HPS SDRAM controller?
VHDL Postfit Simulation Not Supported for Arria V and Cyclone V Designs with Hard Memory Controller
Is DDR2 SDRAM with HPS Hard Controller supported in Arria V SoC Devices?
Cannot Generate DDR3 RDIMM IP for Stratix IV or Stratix V with RC8–RC15 Set to Non-Zero Values
DQS# Enable Option Must be Enabled for LPDDR2 Interfaces
Default tCCD for LPDDR2 Devices Hard Codes to 2 Cycles
Low Frequency Limit for DDR2 and LPDDR2 on Arria V and Cyclone V Devices
Memory Controller May Become Unresponsive for LPDDR2 Interfaces Using Deep Power-Down Mode
Is the Burst Chop 4 (BC4) support in Arria 10 External Memory Interface IP?
How do I resolve Arria 10 External Memory Interfaces DDR4 IP read capture timing violations ?
Arria V and Cyclone V Devices May Display Small DQS Enable Windows
Simulation of Arria 10 Designs With Questa Advanced Simulator Version 10.4b May Hang Under Certain Circumstances
Error Message for Auto Power Down Cycles Does Not Indicate Valid Range
Controller Bonding is Not Available in the Hard Memory Interface
Timing Closure for Soft LPDDR2 Interfaces May Not be Robust
Simulation Fails with PLL Clocks Out of Synchronization for UniPHY External Memory Interfaces
Is there a problem when simulation ALTDQ_DQS2 megafunctions generate by the Quartus II version 12.0?
Some Arria 10 EMIF Designs May Fail Simulation with NCSim and Riviera-PRO
Why are the timing margins the same values for all corners when performing Report DDR in TimeQuest for Arria 10 external memory interfaces?
Why is there a mismatch between the local Avalon interface data width and memory interface data width when generating UniPHY based DDR2 SDRAM, DDR3 SDRAM, QDRII SRAM and RLDRAMII controller IPs?
Why is the Reserved Value in the Altera PHYLite Dynamic Reconfiguration Address Map different during simulation than the one published in the user guide?
Why is Synchronizer Identification assignment for UniPHY based QDRII controller ignored by fitter?
Why are there missing Hex files when I simulate DDR3 SDRAM Controller with UniPHY?
Error (10231): Verilog HDL error at <variation_name>_memphy_top.v(305): value cannot be assigned to input "pll_mem_clk"
Can I use Report DDR for ALTDQ_DQS2 megafunction?
Error (175020): Illegal constraint of pin to the region : no valid locations in region
Error: Node instance "encoder_inst" instantiates undefined entity "alt_mem_ddrx_ecc_encoder_32"
Critical Warning (19028): HPS DDR oct_rzqin pin is placed in a location not supported by HPS Early IO release. If you plan to use Early IO release, place the oct_rzqin in the IO bank 2K.
Why do I see a Qsys warning for the pll_sharing conduit even when the PLL sharing mode option is set to 'No Sharing' in the UniPHY Megacore settings?
External Memory Interface Handbook: Known Issues
Is there any issue with DDR SDRAM, DDR2 SDRAM and DDR3 SDRAM High Performance Controller or High Performance Controller II in Arria II GX devices which may cause hardware failure?
Does the UniPHY-based DDR3 controller support dual-slot, quad-rank DDR3 RDIMM or UDIMM?
Internal Error: Sub-system: EMIF, File: /quartus/periph/emif/emif_gen6.cpp, Line: 832
Warning: Ignored filter at instance_name_p0.sdc(675): {instance_name_clkout[0]} {instance_name_clkout[1]} could not be matched with a clock
Why do I get Burst Chop when accesing DDR3 SDRAM using Altmemphy based DDR3 SDRAM Controller?
Why is the memory reset output port unconstrained in the memory controller?
Timing-Related Warning Messages for QDR II and QDR II+ SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY When Sharing PLLs on Stratix V Devices
Example Project Fails to Simulate When HardCopy Compatibility is Enabled for UniPHY External Memory Interfaces
Clock mem_cq_n Not Used for QDR Interfaces on Arria V and Cyclone V
Timing-Related Warning Messages for DDR2 and DDR3 SDRAM Controller with UniPHY When Sharing PLLs on Stratix V Devices
Some DDR2 and DDR3 EMIF Designs Targeting Arria 10 Devices May Fail Simulation with NCSim and Riviera-PRO.
DDR2 and DDR3 Designs Using Hard Memory Controller May Not Close Timing on Arria V and Cyclone V Devices
Possible Timing Violations with Ping Pong PHY on Arria 10 Devices
Error May Occur When Generating Hard Memory Controller in Qsys
Change to tWPRE Timing Might Cause Failure for DDR2 and DDR3 Interfaces on Arria V and Cyclone V Devices
Possible Read/Write Errors for DDR2 and DDR3 Hard Memory Controllers on Arria V and Cyclone V Devices at Low Vcc and Extreme Temperatures
RTL Modification Required for Top/Bottom Bonding on Arria V and Cyclone V Devices
Possible Syntax Error When Running Abstract PHY Simulation with ModelSim and Tcl
Possible Timing Closure Difficulty for QDR II Interfaces on Arria 10 Devices
Simulation of Arria 10 Designs With Abstract PHY May Hang Under Certain Circumstances
DDR3 Interfaces with Multiple mem_ck signals May Produce No-Fit Errors
ODT Signal Not Functioning Correctly for DDR2 and DDR3 Hard Memory Interfaces Targeting Arria V or Cyclone V Devices
Higher Delays and Skews Expected for UniPHY External Memory Interfaces Corner I/Os in Stratix V Devices
Stratix V QDR II and QDR II+ SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY Memory Interfaces May Exhibit Write Timing Failure
How can the auto-precharge feature of the Intel® Stratix® 10 DDR4 hard memory controller be used to achieve the highest memory bandwidth?
Why doesn't the mmr_slave_readdatavalid signal de-assert when accessing the MMR ECC register?
What are the VREF requirements for a DDR4 interface using the Arria 10 or Stratix 10 External Memory Interfaces IP ?
How should the CKE signal be terminated for DDR3 and DDR4 interfaces?
What is the behavior of the traffic generator status signals in the Intel® Arria® 10 and the Intel Stratix® 10 EMIF IP example design?
Why doesn't the Intel® Stratix® 10, Intel Arria® 10 and Intel Cyclone® 10 EMIF IP calibration sequencer start calibration on the second EMIF IP if the first EMIF IP in the same I/O column fails calibration?
Why doesn't the Intel® Arria® 10 and the Intel Stratix® 10 QDR-IV IP issue burst accesses?
Why doesn't the Intel® Arria® 10 HPS EMIF and Stratix® 10 HPS EMIF IP generate a simulation example design directory?
Why doesn't the Intel® Arria® 10 or the Intel Stratix® 10 DQ/DQS x4 configuration follow the pin-out placement documentation and the DQ/DQS Pins view in the Intel Quartus® Prime Pin Planner?
Why do I see the message "Connection between avalon_master.writedata and avl.avl_wdata must be width of [8,16,32,64,128,256,512,1024] with the DDR2(3) SDRAM Controller with UniPHY?
Simulation Fails for UniPHY External Memory Interfaces with “Undefined System Task Call” Error
Can I create my own customer preset when using DDR2 and DDR3 SDRAM controller with UniPHY?
Possible No Fit Errors on Cyclone V HPS Devices
Calibration May Fail on Some DQS Groups for External Memory Interfaces Targeting Some Arria V Devices
Possible Timing Failure on Certain Paths in Designs Targeting Cyclone V Devices
Simulation Fails for UniPHY External Memory Interfaces when Generating VHDL for Designs Using Nios II-based Sequencer
How to share OCT between QDRII and QDRII+ SRAM Controller with UniPHY and DDR3 SDRAM Controller with ALTMEMPHY?
Possible VHDL Simulation Failure with ModelSim-SE on Arria 10 Devices
DQS Tracking Disabled Below 667 MHz For Some Arria 10 Devices
Driver Margining Not Compatible with Periodic OCT Recalibration in Arria 10 EMIF IP
Timing Closure for Hard LPDDR2 Interfaces May Not be Robust in Cyclone V SoC Devices
How should I connect OCT calibratoin pins (Rup and Rdn) in Altera DDR/DDR2/DDR3 High Perfomance Memory Controller design?
Why my DDR3 HMC example designs targeting Arria V devices with C5 speed grade at 533MHz failed timing?
Error (332000): can't read "local_pll_driver_core_clk": no such variable
What is different between Dynamic ODT and Dynamic OCT when interfacing DDR3 SDRAM with Stratix III or Stratix IV FPGAs?
Why can't some DDR3 HMC control registers be read or written by the CSR interface?
Are there any issues with the DDR/DDR2 specification for Cyclone II C7 and C8 speed grades that were published in AN 361: Interfacing DDR & DDR2 SDRAM With Cyclone II Devices version 1.0?
Stratix V Device Handbook: Known Issues
Error: Bidirectional I/O uses parallel termination, but does not have dynamic termination control connected
Is there an issue after hard memory controller design without specific INI file being programmed on Arria V ES device ?
Why did my DDR3 UniPHY example design fail simulation?
Unable to establish a connection because no memory interface targets exist on the linked device
Is there any knonw issue for simulation StratixIII Altmemphy DDR2?
Why I am seeing the following warnings when I try to run RTL simulation using 3rd party DDR3 vendor model in Modelsim?
Does the Max 10 UniPHY IP support SDR SDRAM or SRAM?
Why do I see the outdated files in the IP core summary of the compilation report?
Error (175005): Could not find a location with: RST_SRC_ID of &lt;value&gt;
Are there any know issues with AltMemPHY IP with mutliple rank external memory systems?
Error: missing operand at _@_ in expressin "_@_/1000.0"
EMIF Debug Toolkit Not Functional for Interfaces Targeting HPS Hard Memory Controller in Cyclone V SoC Devices
Certain I/O Pins Should be Grounded for Cyclone V Hard Memory Controller Operation
LPDDR2 Interfaces on Arria V SoC Devices May Fail Postamble Timing
TimeQuest May Incorrectly Report Timing Failure for Hard Memory Interface on HPS Subsystem for Cyclone V SoC Devices
Hardware Failure with LPDDR2 Hard Memory Controller on Cyclone V Devices at 300MHz and 333MHz
ECC Enabled Automatically in Cyclone V SoC HPS Devices
Deep Power Down Issue With LPDDR2 Interfaces on Cyclone V Devices
Are there any concern on DDR timing using Altera EMIF (External Memory Interface) IP if my design fails DCD (Duty Cycle Distortion) compliance testing?
Some DDR4 LRDIMM Hardware Configurations May Fail Calibration
Simulation Example Design Fails and Produces Warnings
For some MAX 10 device designs, the Fitter causes an abnormal exit during the Fitter stage when listen_to_nsleep_signal is set
Arria V and Cyclone V Soft Controllers May Not Meet Frequency Targets if CSR or ECC Enabled
Why do I see data errors on my HPS LPDDR2 interface?
Are there any factors that can affect the efficiency performance of the UniPHY LPDDR2 IP?
What information does the Efficiency Monitor display in the EMIF Toolkit?
Self-refresh Not Working Properly for Single-rank DDR3 DIMMs
ECC and CSR Designs May Fail in Simulation or Hardware
Simulation Fails When Enable Auto Error Correction Option Enabled
NativeLink Simulation in UniPHY External Memory Interfaces fail for VHDL Output
VHDL-Only Simulation Not Supported for QDR II and QDR II+ SRAM Controller with UniPHY and RLDRAM II Controller with UniPHY
Altera PHYLite for Parallel Interfaces IP Core User Guide: Known Issues
In DDR2 and DDR3 SDRAM Controller with UniPHY, Example Designs Without DM Pins Enabled Will Fail
Error Can Occur When Using Multiple EMIFs in a Single Column and Sharing RZQ Pins
Incorrect Pin Mapping for DDR3 LRDIMM and LPDDR3 in Arria 10 EMIF
PLL Master Required for Simulation of PLL Slave for UniPHY External Memory Interfaces
Arria 10 EMIF IP for QDR-IV Using Address Inversion May Fail in Hardware
EMIF Toolkit Error May Occur for Multiple Interfaces in the Same Column with the Same Interface ID
No Error Message is Displayed for Invalid Configuration
VHDL Simulation of Arria 10 EMIF IP with Riviera-PRO May Fail to Progress Under Some Circumstances
Enable Avalon-MM Byte-Enable Signal Option Not Functional for RLDRAM II Controller with UniPHY
DDR2 Interfaces on Cyclone V SoC Devices May Fail Read Capture Timing
Simulation of Example Designs Can Fail or Produce Warnings for UniPHY External Memory Interfaces
RLDRAM II Controller with UniPHY Simulation fails in Riviera-PRO
Fitter Error When Compiling DDR2 Designs Below 240MHz in DDR2 and DDR3 SDRAM Controller with UniPHY
Example Design Simulation for UniPHY External Memory Interfaces May Fail in NC Sim
Full-rate QDR II and RLDRAM II Are Not Supported for Arria V
Cyclone V Hard Memory Interface Does Not Provide Fitter Support
Is there any issue when instance the DDR3 hard IP core?
False Timing Failures in QDR-IV Interfaces on Arria 10 Devices
Why DDR3 ODT fails in simulation with denali?
Error May Occur When Simulating VHDL Designs With MMR Enabled Using VCS-MX
For EMIF Interfaces on Arria 10 Devices, the Duplicate Qsys Button results in an Error Message
Why is the efficiency of DDRx UniPHY controller version 11.0 worse than the efficiency of the 10.1 version of the controller?
How can I make parallel On Chip Termination assignment to the CQ and CQn bi-directional pins of the Legacy QDRII SRAM Controller in Stratix II devices?
Do I have to connect VREF pin of the I/O bank where mem_clk pins are located when implementing ALTMEMPHY based IP in Arria II GX devices?
Why do the DQS and DQSn signals generated by the DDR SDRAM and DDR2 SDRAM High-Performance Controllers I for write operations have an additional pulse at the end of a write burst?
Can F1152 and F1517 packages in Stratix IV GX devices support x32/x36 DQS/DQ group?
Why does my ALTDQ_DQS2 design have conflicting warning messages?