External Memory Interfaces IP - Support Center

Welcome to the External Memory Interface (EMIF) support page! Here you will find information regarding Intel® Agilex™, Intel® Stratix® 10, Intel® Arria® 10, and Intel® Cyclone® 10 FPGAs on how to plan, design, implement, and verify your external memory interfaces. You will also find debug, training, and other resource materials on this page.

This page is set up to walk you through the design process from start to finish.

For support resources regarding other FPGAs, search within the following links: Documentation Archive, Training Courses, Videos and Webcasts, Design Examples, and Knowledge Base.

How Do I Select a Device?

Two tools are available to help you select an Intel® FPGA based on your memory requirements:

	EMIF Device Selector	EMIF Spec Estimator
Features	Determines memory interfaces needed to achieve a desired bandwidth Calculates bandwidth based on selected memory configurations Displays all Intel® Agilex™, Intel® Stratix® 10, and Intel® Arria® 10 FPGAs supporting selected memory interfaces	Determines required Intel® FPGA device family and speed grade needed to achieve desired performance Displays maximum frequency and DQ width available based on memory selections
Device Support	Intel® Agilex® FPGAs Intel® Stratix® 10 FPGAs Intel® Arria® 10 FPGAs	All Intel® FPGAs
Resources	Download EMIF Device Selector View EMIF Device Selector Video	Launch EMIF Spec Estimator View EMIF Spec Estimator Video

How Do I Select an External Memory Intellectual Property (IP)?

To learn about the various memory intellectual property (IP) available, refer to the following online training curriculum:

Training Course	Description
Introduction to Memory Interfaces IP in Intel® FPGA Devices	This course covers the different external memory interface options available, as well as the architectural and hard memory controller features for Intel® Stratix® 10 and Intel® Arria® 10 FPGAs
High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX Devices: Introduction, Architecture	This course covers the benefits of integrating High Bandwidth Memory into the Intel Stratix 10 MX FPGA devices, features and options for the hardened HBM controller, and how to generate the HBM2 IP
High Bandwidth Memory (HBM2) Interfaces in Intel Stratix 10 MX Devices: HBMC Features	This course covers the features and options for the hardened HBM controller, and the Arm* AMBA 4 AXI interface between the controller and user logic
SoC Hardware Overview: Interconnect and Memory	This course covers the features of the Hard Processor Subsystem (HPS) SDRAM and the AMBA AXI bridge architecture

User Guides

Intel® Agilex™ Devices

Intel® Stratix® 10 Devices

EMIF IP User Guide

External Memory Interfaces Intel® Stratix® 10 FPGA IP User Guide

Design Example User Guide

External Memory Interfaces Intel® Stratix® 10 FPGA IP Design Example User Guide

Release Notes

External Memory Interfaces Intel® Stratix® 10 FPGA IP Core Release Notes

Pin-Out Files

Intel ®Stratix® 10 Device Pin-Out and EMIF Address/Command Pin-Out

Intel® Arria® 10 Devices

EMIF IP User Guide

External Memory Interfaces Intel® Arria® 10 FPGA IP User Guide

Design Example User Guide

External Memory Interfaces Intel® Arria® 10 FPGA IP Design Example User Guide

Release Notes

Intel Arria® 10 FPGA IP Core Release Notes

Pin-Out Files

Intel® Arria® 10 Device Pin-Out and EMIF Address/Command Pin-Out

Intel® Cyclone® 10 Devices

EMIF IP User Guide

External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP User Guide

Design Example User Guide

External Memory Interfaces Intel® Cyclone® 10 GX FPGA IP Design Example User Guide

Release Notes

External Memory Interfaces Intel ®Cyclone® 10 FPGA IP Core Release Notes

Pin-Out Files

Intel® Cyclone ®10 Device Pin-Out and EMIF Address/Command Pin-Out

Intel® FPGA PHY Lite

PHY Lite for Parallel Interfaces Intel® FPGA IP Core User Guide

Intel FPGA HBM2 User Guide

High Bandwidth Memory (HBM2) Interface Intel® FPGA IP User Guide

Where Do I Find Information on the EMIF IP?

For information regarding the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following External Memory Interfaces IP User Guides:

Please refer to 'User Guides' Section

How Do I Generate the EMIF IP?

For detailed information regarding External Memory Interface (EMIF) Intellectual Property (IP) parameters, refer to the following protocol-specific sections within the following EMIF IP User Guides:

	Intel® Stratix® 10	Intel® Arria® 10	Intel® Cyclone® 10	Intel® Agilex®
EMIF IP Parameter Descriptions	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 HBM2	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3	DDR4 QDR-IV

Note: For more information on 'How Do I Generate IP', refer to the 'User Guide' and 'Training Course and Video' sections.

How Do I Perform Functional Simulation?

For detailed information on simulating the External Memory Interface (EMIF) Intellectual Property (IP), refer to the following section within the EMIF IP User Guides:

For instructions on how to generate an EMIF simulation design example and how to run simulations using the ModelSim*-Intel^® FPGA simulation software, refer to the following sections within the EMIF IP Design Example User Guides:

For information on how to verify an EMIF design, refer to the 'Training Courses and Video' section for the 'Verifying Memory Interfaces IP' course.

Where Do I Find Information on FPGA Resource and Pin Placement?

For detailed External Memory Interface (EMIF) pin information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

	Intel® Stratix® 10	Intel® Arria® 10	Intel® Cyclone® 10	Intel® Agilex™
EMIF Pin and Resource Planning	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3	DDR4 QDR-IV

Intel® Stratix® 10

Intel® Arria® 10

Intel® Cyclone® 10

Intel® Agilex™

EMIF Pin and Resource Planning

DDR3
LPDDR3

DDR4
QDR-IV

For simplified I/O placement refer to the Interface Planner for an easy-to-use drag-and-drop tool available in the Intel® Quartus® Prime Pro Edition software for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. Refer to the following videos for information on how to use the Interface Planner and its benefits:

For more information on Interface Planner for resource location assignments, refer to the following online training curriculum:

Training Course	Description
Fast & Easy I/O System Design with Interface Planner	This course covers how to implement a design resource floorplan using Interface Planner

Additional Resources

What is Ping Pong PHY?

Ping Pong PHY allows two memory interfaces to share Address and Command buses. This is supported for DDR3 and DDR4 protocols and for Stratix® V, Intel® Arria® 10, and Intel® Stratix® 10 FPGAs. Refer to the following video for information on the concept of Ping Pong PHY, its benefits, and an analysis of simulation results:

DDR4 Ping Pong PHY Video

Where Do I Find Information on PHYLite?

The PHYLite IP allows you to build custom memory interface PHY blocks for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. For detailed information about the PHYLite IP, refer to the following user guide:

PHYLite for Parallel Interfaces IP Core User Guide

For detailed information on how to properly assign pinouts for PHYLite based on different DQ/DQS group sizes, refer to the following video:

PHYLite Group Pin Placement Video (Note: The video is also applicable to Intel® Stratix® 10 devices.)

The PHYLite IP supports many different I/O standards and termination values on input and output buffers for Intel® Arria® 10 and Intel® Stratix® 10 FPGAs. Refer to the following video for infroamtion on how to create an On-Chip-Termination (OCT) block and how to associate it with the terminated I/O buffer in the PHYLite IP:

OCT Block for PHYLite Video

Where Do I Find Information on Board Layout and Design?

For detailed External Memory Interface (EMIF) board layout and design information, refer to the following protocol-specific sections within the following EMIF Intellectual Property (IP) User Guides:

	Intel® Stratix® 10	Intel® Arria® 10	Intel® Cyclone® 10	Intel® Agilex™
EMIF Board Design Guidelines	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3	DDR3 DDR4 QDR II/II+/II+ Xtreme QDR-IV RLDRAM3 LPDDR3	DDR3 LPDDR3	DDR4 QDR-IV

Intel® Stratix® 10

Intel® Arria® 10

Intel® Cyclone® 10

Intel® Agilex™

EMIF Board Design Guidelines

DDR3
LPDDR3

DDR4
QDR-IV

How Do I Perform Board/Channel Simulation?

For information on measuring write-and-read Intersymbol Interference (ISI) and Crosstalk, arranging Command, Address, Control and Data pins, and I/O bank placement restrictions, refer to the following guidelines:

Intel® Arria® 10 Device Channel Simulation Guidelines
Calculating Channel Loss from DDRx Simulation Guidelines (Note: The Intel® Arria® 10 channel guidelines is also applicable to Intel® Stratix® 10 devices)

How Do I Calculate Board Skew and Channel Loss?

Two tools are available to help you calculate board skew and channel loss:

	Board Skew Parameter Tool	Channel Loss Calculation Tool
Features	Calculates board skew due to PCB traces and multi-rank designs	Calculates channel loss due to Intersymbol Interference (ISI) and Crosstalk on Command, Address, Control, and Data signals
Support	Intel® Arria® 10 and Intel® Stratix® 10 FPGAs All memory protocols	Intel® Arria® 10 and Intel® Stratix® 10 FPGAs DDR memory protocols Compatible with Mentor Graphics HyperLynx Signal Integrity software only
Resources	Download Board Skew Parameter Tool View Board Skew Parameter Tool Video	Download Channel Loss Tool

Where Do I Find Information on Timing Closure?

For information regarding External Memory Interface (EMIF) timing closure, refer to the following section within the EMIF Intellectual Property (IP) User Guides:

How Do I Debug My External Memory Interface Design?

For information regarding debugging the external memory interface (EMIF) intellectual property (IP), refer to the following section within the EMIF IP User Guides:

The main tool available for debug is the EMIF Debug Toolkit:

	EMIF Debug Toolkit
Features	Displays pre and post calibration margins per DQS group and DQ pin Generates read/write eye diagrams per DQ pin (2-D eye diagram) Allows customizable real-time traffic generator for test/debug (Traffic Generator 2.0) Captures read/write margins during user-mode traffic (Driver Margining)
Support	Compatible with EMIF design example projects and custom EMIF designs containing one or more memory interfaces Supports all memory protocols
Accessibility	Accessible through the Intel® Quartus® Prime software (Tools > System Debugging Tools > External Memory Interface Toolkit)

How Do I Use the EMIF Debug Toolkit?

For step-by-step instructions on how to daisy-chain multiple memory interfaces for compatibility with the EMIF Debug Toolkit, refer to the following user guide:

Debugging Multiple Memory Interfaces Guide

The Read/Write 2-D Eye Diagram feature available in the EMIF Debug Toolkit generates read-and-write eye diagrams for each data pin. Refer to the following video for information on important voltage reference parameters during the EMIF IP generation process and how to use the 2-D Eye Diagram feature:

2-D Eye Diagram Video

The Traffic Generator 2.0 allows you to test and debug your external memory interface through customizable traffic and test patterns. Refer to the following guide and videos for detailed information on how to use the Traffic Generator 2.0 feature:

Traffic Generator 2.0 Guide
Traffic Generator 2.0 Video (comming soon)

The Driver Margining feature allows you to capture read-and-write margining data per pin during user-mode traffic. Refer to the following videos for information on the differences between driver margining and calibration margining, and instructions on how to use the Driver Margining feature:

For information on how to debug an EMIF design, refer to the following online training curriculum:

Training Course	Description
On-Chip Debugging of Memory Interfaces IP in Intel® Arria® 10 Devices	This course covers how to perform debug using the EMIF Toolkit or On-Chip Debug Toolkit, how to use Traffic Generator 2.0, and configure multiple memeory interface designs for compatibility with these debug tools

Where Can I Find Information Regarding Optimizing Controller Performance?

For information regarding controller performance and efficiency, refer to the following section within the External Memory Interfaces (EMIF) Intellectual Property (IP) User Guides: