JESD204B and JESD204C IP Core Support Center
The JESD204B and JESD204C FPGA IP core support center provides information on how to select, design, implement and debug JESD204B and JESD204C links. This page is organized into categories that align with a JESD204B and JESD204C system design flow from start to finish.
The JESD204B and JESD204C IP Core Support Center provides resources for Agilex™ 7, Agilex™ 5, Stratix® 10, Arria® 10, and Cyclone® 10 devices.
Get additional support for Agilex™ 7 FPGA Interface Protocol Design Journey, and Agilex™ 5 FPGA Interface Protocol Design Journey, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.
Getting Started
1. Device and IP Selection
Which FPGA Family Should I Use?
Table 1 - JESD204B FPGA IP Core Performance
Device Family | PMA Speed Grade | FPGA Fabric Speed Grade | Data Rate | Link Clock fMAX (MHz) | |
---|---|---|---|---|---|
Enable Hard PCS (Gbps) | Enable Soft PCS (Gbps) 1 | ||||
Agilex™ 7 (F-Tile) | 1 | -1 | Not supported | 2.0 to 20.0 | data_rate/40 |
-2 | Not supported | 2.0 to 19.2 | data_rate/40 | ||
2 | -2 | Not supported | 2.0 to 19.2 | data_rate/40 | |
-3 | Not supported | 1.0 to 16.7 | data_rate/40 | ||
3 | -3 | Not supported | 2.0 to 16.7 | data_rate/40 | |
Agilex™ 7 (E-Tile) | 2 | -2 | Not supported | 2.0 to 17.4 | data_rate/40 |
3 | -2 | Not supported | 2.0 to 17.4 | data_rate/40 | |
-3 | Not supported | 2.0 to 16.0 | data_rate/40 | ||
Agilex™ 5 E-Series (Device Group B) | -4 | Not supported | 15.50* | data_rate/40 | |
-5 | Not supported | 14.90* | data_rate/40 | ||
-6 | Not supported | 12.70* | data_rate/40 | ||
Stratix® 10 (L-Tile and H-Tile) | 1 | 1 | 2.0 to 12.0 | 2.0 to 16.02 | data_rate/40 |
2 | 2.0 to 12.0 | 2.0 to 14.0 | data_rate/40 | ||
2 | 1 | 2.0 to 9.83 | 2.0 to 16.02 | data_rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 14.0 | data_rate/40 | ||
3 | 1 | 2.0 to 9.83 | 2.0 to 16.02 | data_rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 14.0 | data_rate/40 | ||
3 | 2.0 to 9.83 | 2.0 to 13.0 | data_rate/40 | ||
Stratix® 10 (E-Tile) | 1 | 1 | Not supported | 2.0 to 16.02 | data_rate/40 |
2 | Not supported | 2.0 to 14.0 | data_rate/40 | ||
2 | 1 | Not supported | 2.0 to 16.02 | data_rate/40 | |
2 | Not supported | 2.0 to 14.0 | data_rate/40 | ||
3 | 3 | Not supported | 2.0 to 13.0 | data_rate/40 | |
Arria® 10 | 1 | 1 | 2.0 to 12.0 | 2.0 to 15.0 (2, 3) | data rate/40 |
2 | 1 | 2.0 to 12.0 | 2.0 to 15.0 (2, 3) | data rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 15.0 (2, 3) | data rate/40 | ||
3 | 1 | 2.0 to 12.0 | 2.0 to 14.2 (2, 4) | data rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 14.2 (2, 5) | data rate/40 | ||
4 | 3 | 2.0 to 8.83 | 2.0 to 12.5 (6) | data rate/40 | |
Cyclone® 10 GX | <Any supported speed grade> | -5 | 2.0 to 9.8 | 2.0 to 9.8 | data rate/40 |
-6 | 2.0 to 6.25 | 2.0 to 9.8 | data rate/40 |
Table 2 - JESD204C FPGA IP Core Performance
Device Family | PMA Speed Grade | FPGA Fabric Speed Grade | Data Rate | Link Clock fMAX (MHz) | |
---|---|---|---|---|---|
Enable Hard PCS (Gbps) | Enable Soft PCS (Gbps) | ||||
Agilex™ 7 (F-Tile) | 1 | -1 | Not supported | 5 to 32.44032 | data_rate/40 |
-2 | Not supported | 5 to 32.44032 | data_rate/40 | ||
2 | -1 | Not supported | 5 to 28.8948* | data_rate/40 | |
-2 | Not supported | 5 to 28.8948* | data_rate/40 | ||
-3 | Not supported | 5 to 24.33024 | data_rate/40 | ||
3 | -3 | Not supported | 5 to 17.4 | data_rate/40 | |
Agilex™ 7 (E-Tile) | 1 | -1 | Not supported | 5 to 28.9 | data_rate/40 |
2 | -2 | Not supported | 5 to 28.3 | data_rate/40 | |
-3 | Not supported | 5 to 25.6 | data_rate/40 | ||
3 | -2 | Not supported | 5 to 17.4 | data_rate/40 | |
-3 | Not supported | 5 to 17.4 | data_rate/40 | ||
Agilex™ 5 E-Series (Device Group B) | -4 | Not supported | 17.16 | data_rate/40 | |
-5 | Not supported | 17.16 | data_rate/40 | ||
-6 | Not supported | 17.16 | data_rate/40 | ||
Agilex™ 5 E-Series (Device Group A) / D-Series | -1 | Not supported | 28.1 | data_rate/40 | |
-2 | Not supported | 28.1 | data_rate/40 | ||
-3 | Not supported | 28.1 | data_rate/40 | ||
Stratix® 10 (E-Tile) | 1 | -1 | Not supported | 5 to 28.9 | data_rate/40 |
-2 | Not supported | 5 to 25.6 | data_rate/40 | ||
2 | -1 | Not supported | 5 to 28.3 | data_rate/40 | |
-2 | Not supported | 5 to 25.6 | data_rate/40 | ||
3 | -1 | Not supported | 5 to 17.4 | data_rate/40 | |
-2 | Not supported | 5 to 17.4 | data_rate/40 | ||
-3 | Not supported | 5 to 17.4 | data_rate/40 |
*Maximum data rate may reduce with ECC enable. Please refer to Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information.
1. Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs an additional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional 10–20% increase in resource utilization.
2. Refer to the Arria® 10 and Stratix® 10 Device Datasheet for the maximum data rate supported across transceiver speed grades and transceiver power supply operating conditions.
3. When using Soft PCS mode at 15.0 Gbps, the timing margin is very limited. You are advised to enable high fitter effort, register duplication, and register retiming to improve timing performance.
4. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is up to 12.288 Gbps.
5. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 11.0 Gbps.
6. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 10.0 Gbps.
2. Design Flow and IP Integration
Where Can I Find Information on IP integration?
Agilex™ 7 Devices
- AN 901: Implementing Analog-to-Digital Converter Dual Link Design with Agilex™ 7 FPGA E-Tile JESD204C RX IP
- AN 967: Multiple Device Synchronization in Digital Phased Array System
Stratix® 10 Devices
- AN804: Implementing Synchronized ADC Multi-link Designs with Stratix® 10 JESD204B RX IP Core
- AN804: Implementing Unsynchronized ADC Multi-link Designs with Stratix® 10 JESD204B RX IP Core
Arria® 10 Devices
3. Board Design and Power Management
Pin Connection Guidelines
Agilex™ 7 Devices
Agilex™ 5 Devices
Stratix® 10 Devices
Arria® 10 Devices
Cyclone® 10 Devices
Schematic Review
Agilex™ 7 Devices
Agilex™ 5 Devices
Stratix® 10 Devices
Cyclone® 10 Devices
Arria® 10 Devices
Board Design Guidelines
- Agilex™ 7 Device Family High-Speed Serial Interface Signal Integrity Design Guidelines
- AN 886: Agilex™ 7 Device Design Guidelines
- Agilex™ 5 FPGAs and SoCs Device Design Guidelines
- AN 766: Stratix® 10 Devices, High-Speed Signal Interface Layout Design Guideline
- AN 613: PCB Stackup Design Considerations for FPGAs
- AN 114: Board Design Guidelines for Intel® Programmable Device Packages
- Board Design Guidelines Solutions
- Board Layout Test
Power Management
- Agilex™ 7 Power Management User Guide
- Agilex™ 5 FPGAs and SoCs Power Management User Guide
- AN 910: Agilex™ 7 Power Distribution Network Design Guidelines
- Early Power Estimator (EPE) and Power Analyzer
- AN 750: Using the FPGA PDN Tool to Optimize Your Power Delivery Network Design
- Device-Specific Power Deliver Network (PDN) Tool 2.0 User Guide
Thermal Power Management
Agilex™ 7 Devices
Stratix® 10 Devices
Power Sequencing
Agilex™ 7, Agilex™ 5, Stratix® 10, Cyclone® 10, and Arria® 10 Devices
4. Interoperability and Standards Testing
JESD204B FPGA IP Hardware Checkout Reports
Agilex™ 7 Devices
- AN 976: JESD204C FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Agilex™ 7 F-Tile Devices
- AN 876: JESD204C FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Agilex™ F-Tile Devices
- AN 960: JESD204C FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Agilex™ 7 E-Tile Devices
Stratix® 10 Devices
JESD204B
- AN 905: JESD204B FPGA IP and ADI AD9213 Interoperability Report for Stratix® 10 Devices
- AN 915: JESD204B FPGA IP and ADI AD9208 Interoperability Report for Stratix® 10 E-Tile Devices
- AN 890: JESD204B FPGA IP and ADI AD9174 Interoperability Report for Stratix® 10 L-Tile Devices
- AN 823: FPGA JESD204B IP Core and ADI AD9625 Hardware Checkout Report for Stratix® 10 Devices
- AN 832: FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report for Stratix® 10 Devices
- AN 833: Stratix 10® GX 16-Lane RX JESD204B-ADC12DJ3200 Interoperability Reference Design
JESD204C
- AN 909: JESD204C FPGA IP and TI ADC12DJ5200RF Interoperability Report for Stratix® 10 Devices
- AN 916: JESD204C FPGA IP and ADI AD9081/AD9082 MxFE* Interoperability Report for Stratix® 10 E-Tile Devices
- AN 927: JESD204C FPGA IP and ADI AD9081 MxFE* ADC Interoperability Report for Stratix® 10 E-Tile Devices
- AN 949: JESD204C FPGA IP and ADI AD9081 MxFE* DAC Interoperability Report for Stratix® 10 E-Tile Devices
Arria® 10 Devices
- AN 710: FPGA JESD204B MegaCore Function and ADI AD9680 Hardware Checkout Report
- AN 712: FPGA JESD204B MegaCore Function and ADI AD9625 Hardware Checkout Report
- AN 749: FPGA JESD204B IP Core and ADI AD9144 Hardware Checkout Report
- AN 753: FPGA JESD204B IP Core and ADI AD6676 Hardware Checkout Report
- AN 779: FPGA JESD204B IP Core and ADI AD9691 Hardware Checkout Report
- AN 785: FPGA JESD204B IP Core and ADI AD9162 Hardware Checkout Report
- AN 792: FPGA JESD204B IP Core and ADI AD9371 Hardware Checkout Report
- AN 810: FPGA JESD204B IP Core and ADI AD9208 Hardware Checkout Report
5. Design Examples and Reference Designs
Table -3: Consolidated JESD204B/C Resources
JESD204B FPGA IP | JESD204C FPGA IP | F-Tile JESD204C FPGA IP | F-Tile JESD204B FPGA IP | GTS JESD204C FPGA IP | ||
---|---|---|---|---|---|---|
IP User Guide | General | JESD204B FPGA IP User Guide | JESD204C FPGA IP User Guide | F-Tile JESD204C FPGA IP User Guide | F-Tile JESD204B FPGA IP User Guide | GTS JESD204C FPGA IP User Guide |
Design Example User Guide | Agilex™ 7 | JESD204B Agilex™ FPGA IP Design Example User Guide | JESD204C Agilex™ FPGA IP Design Example User Guide | F-Tile JESD204C FPGA IP Design Example User Guide | F-Tile JESD204B FPGA IP Design Example User Guide | |
Agilex™ 5 | GTS JESD204C FPGA IP Design Example User Guide | |||||
Stratix® 10 | JESD204B Stratix® 10 FPGA IP Design Example User Guide | JESD204C Stratix® 10 FPGA IP Design Example User Guide | ||||
Cyclone® 10 | JESD204B Cyclone® 10 GX FPGA IP Design Example User Guide | |||||
Arria® 10 | JESD204B Arria® 10 FPGA IP Design Example User Guide | |||||
Standard | JESD204B FPGA IP Design Example User Guide: Quartus® Prime Standard Edition |
6. Training Courses and Videos
FPGA Technical Training
Video Title |
Description |
---|---|
This online course provides a broad overview of the JESD204B FPGA IP core. For better understanding of all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification, and followed by a presentation of some of the important features of the JESD204B FPGA IP core. Finally, a data flow of the system is used to describe the functional details of the core. |
FPGA Quick Videos
Video Title |
Description |
---|---|
Agilex™ 7 FPGA F-Tile JESD204C Demo Video | The JESD204B/C standards have been supported on several generations of FPGAs. Watch this demo on how JESD204C works on an Agilex™ 7 FPGA. |
Learn about the interoperability of JESD204B FPGA IP core on the Arria® 10 FPGA with the AD9144 converter from Analog Devices Inc. (ADI). |
|
How to interoperate ADI AD9680 with FPGA JESD204B IP Core on Stratix® V FPGA |
Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B FPGA IP core. |
How to interoperate ADI AD9680 with FPGA JESD204B IP on Stratix® V |
Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B FPGA IP core. |
How to interoperate TI DAC37J84 with FPGA JESD204B MegaCore on Stratix® V FPGA |
Learn about the interoperability of JESD204B FPGA IP core on the Stratix® V FPGA with the DAC37J84 converter from Texas Instruments. |
Learn about JESD204B standard and the JESD204B FPGA IP solution. Find out how you can easily create a design example that works on hardware. |
|
Learn about the interoperability of JESD204B FPGA IP core on the Arria® V FPGA with the DAC37J84 converter from Texas Instruments. |
7. Debug
Tools
Document Title | Description |
---|---|
The objective of this debug FTA example is to help troubleshoot and identify issue related to Altera JESD204B IP Core and resolve it effectively. |
User Guides
Document Title | Supported devices | Description |
---|---|---|
JESD204B FPGA IP User Guide - Chapter 6: JESD204B IP Core Debug Guidelines | Agilex™ 7, Stratix® 10, Arria® 10, Cyclone® 10 GX, Stratix® V, Arria® V, Cyclone® V | These guidelines assist you in debugging JESD204B link issues. |
JESD204B FPGA IP Overview | Agilex™ 9, Agilex ™ 7, Agilex™ 5 | The JEDEC committee created the JESD204 data converter serial interface standard to standardize and reduce the number of data inputs/outputs between high-speed data converters and other devices, such as FPGAs. |
AN 871: Quick Guide for Arria® 10 and Cyclone® 10 GX Transceiver High-Speed Link Tuning | Arria® 10, Cyclone® 10 GX | If high channel loss causes bit error rates (BER) higher than the protocol target BER, you must tune your high-speed links to find optimum equalization values. |
Ethernet Link Inspector User Guide for Stratix® 10 Devices | Stratix® 10 | The Ethernet Link Inspector is an inspection tool that can continuously monitor an Ethernet link that contains an Ethernet IP, which includes Ethernet lane alignment status, clock data recover (CDR) lock, media access controller (MAC) statistics, Forward Error Correction (FEC) statistics, and others. |
Intellectual Property (IP) Core Release Notes
Document Title | Supported devices | Description |
---|---|---|
JESD204B FPGA IP Core Release Notes | Agilex ™ 7, Stratix® 10, Stratix® V, Arria® 10, Arria® V, Cyclone® 10 GX, Cyclone® V | The JESD204B FPGA IP release notes list the changes made in a particular release. |
F-Tile JESD204B FPGA IP Release Notes | Agilex™ 7 | The F-Tile JESD204B FPGA IP release notes list the changes made in a particular release. |
F-Tile JESD204C FPGA IP Release Notes | Agilex™ 7 | Lists the changes made in the F-Tile JESD204C FPGA IP in a particular Quartus® Prime software release. |
GTS JESD204C FPGA IP Release Notes: E-Series Devices | Agilex™ 5 | Lists the changes made in the GTS JESD204C Intel® FPGA IP in a particular Quartus® Prime software release. |
Additional Resources
Document Title | Supported devices |
Description |
---|---|---|
Agilex™ 7, Stratix® 10 Agilex™ 7, Agilex™ 5, Stratix® 10, Arria® 10, Cyclone® 10 GX |
The PHY Lite for Parallel Interfaces Intel® FPGA IP is suitable for simple parallel interfaces. You can use this solution to interface with protocols such as DDR2, LPDDR2, LPDDR, TCAM, Flash, ONFI (synchronous mode), and mobile DDR. |
|
F-tile Architecture and PMA and FEC Direct PHY IP User Guide | Agilex™ 7 | This user guide describes architecture and implementation details for the F-Tile building blocks, physical (PHY) layer IP, PLLs, and clock networks. |
Cyclone® 10 GX Transceiver PHY User Guide | Cyclone® 10 | This user guide provides details about the Intel® Cyclone® 10 GX transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP core. |
Arria® 10 Transceiver PHY User Guide | Arria® 10 | This user guide provides details about the Arria® 10 transceiver physical (PHY) layer architecture, PLLs, clock networks, and transceiver PHY IP. |
L- and H-Tile Transceiver PHY User Guide | Stratix® 10 | The E-tile is a 24-channel, PAM4/NRZ dual-mode transceiver tile that is used in multiple variants of the Stratix® 10 and Agilex™ 7 device families. |