JESD204B and JESD204C IP Core Support Center
The JESD204B and JESD204C FPGA IP core support center provides information on how to select, design, implement and debug JESD204B and JESD204C links. This page is organized into categories that align with a JESD204B and JESD204C system design flow from start to finish.
The JESD204B and JESD204C IP Core Support Center provides resources for Agilex™ 7, Agilex™ 5, Agilex™ 3, Stratix® 10, Arria® 10, and Cyclone® 10 devices.
Get additional support for Agilex™ 7 FPGA Interface Protocol Design, Agilex™ 5 FPGA Interface Protocol Design, and Agilex™ 3 FPGA Interface Protocol Design, step-by-step guided journeys for standard development flows surfacing the key critical resources and documentation.
For other devices, search the Device and Product Support Collections.
Getting Started
1. Device and IP Selection
Which FPGA Family Should I Use?
Table 1 - JESD204B FPGA IP Core Performance
Device Family | PMA Speed Grade | FPGA Fabric Speed Grade | Data Rate | Link Clock fMAX (MHz) | |
---|---|---|---|---|---|
Enable Hard PCS (Gbps) | Enable Soft PCS (Gbps) 1 | ||||
Agilex™ 7 (F-Tile) | 1 | -1 | Not supported | 2.0 to 20.0 | data_rate/40 |
-2 | Not supported | 2.0 to 19.2 | data_rate/40 | ||
2 | -2 | Not supported | 2.0 to 19.2 | data_rate/40 | |
-3 | Not supported | 1.0 to 16.7 | data_rate/40 | ||
3 | -3 | Not supported | 2.0 to 16.7 | data_rate/40 | |
Agilex™ 7 (E-Tile) | 2 | -2 | Not supported | 2.0 to 17.4 | data_rate/40 |
3 | -2 | Not supported | 2.0 to 17.4 | data_rate/40 | |
-3 | Not supported | 2.0 to 16.0 | data_rate/40 | ||
Agilex™ 5 E-Series (Device Group B) | Not supported | 17.16 | data_rate/40 | ||
Agilex™ 3 C-Series | -6 | Not supported | 2.0 to 12.5* | data_rate/40 | |
-7 | Not supported | 2.0 to 12.5* | data_rate/40 | ||
Stratix® 10 (L-Tile and H-Tile) | 1 | 1 | 2.0 to 12.0 | 2.0 to 16.02 | data_rate/40 |
2 | 2.0 to 12.0 | 2.0 to 14.0 | data_rate/40 | ||
2 | 1 | 2.0 to 9.83 | 2.0 to 16.02 | data_rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 14.0 | data_rate/40 | ||
3 | 1 | 2.0 to 9.83 | 2.0 to 16.02 | data_rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 14.0 | data_rate/40 | ||
3 | 2.0 to 9.83 | 2.0 to 13.0 | data_rate/40 | ||
Stratix® 10 (E-Tile) | 1 | 1 | Not supported | 2.0 to 16.02 | data_rate/40 |
2 | Not supported | 2.0 to 14.0 | data_rate/40 | ||
2 | 1 | Not supported | 2.0 to 16.02 | data_rate/40 | |
2 | Not supported | 2.0 to 14.0 | data_rate/40 | ||
3 | 3 | Not supported | 2.0 to 13.0 | data_rate/40 | |
Arria® 10 | 1 | 1 | 2.0 to 12.0 | 2.0 to 15.0(2)(3) | data rate/40 |
2 | 1 | 2.0 to 12.0 | 2.0 to 15.0(2)(3) | data rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 15.0(2)(3) | data rate/40 | ||
3 | 1 | 2.0 to 12.0 | 2.0 to 14.2(2)(4) | data rate/40 | |
2 | 2.0 to 9.83 | 2.0 to 14.2(2)(5) | data rate/40 | ||
4 | 3 | 2.0 to 8.83 | 2.0 to 12.5(6) | data rate/40 | |
Cyclone® 10 GX | <Any supported speed grade> | -5 | 2.0 to 9.8 | 2.0 to 9.8 | data rate/40 |
-6 | 2.0 to 6.25 | 2.0 to 9.8 | data rate/40 |
Table 2 - JESD204C FPGA IP Core Performance
Device Family | PMA Speed Grade | FPGA Fabric Speed Grade | Data Rate | Link Clock fMAX (MHz) | |
---|---|---|---|---|---|
Enable Hard PCS (Gbps) | Enable Soft PCS (Gbps) | ||||
Agilex™ 7 (F-Tile) | 1 | -1 | Not supported | 5 to 32.44032 | data_rate/40 |
-2 | Not supported | 5 to 32.44032 | data_rate/40 | ||
2 | -1 | Not supported | 5 to 28.8948* | data_rate/40 | |
-2 | Not supported | 5 to 28.8948* | data_rate/40 | ||
-3 | Not supported | 5 to 24.33024 | data_rate/40 | ||
3 | -3 | Not supported | 5 to 17.4 | data_rate/40 | |
Agilex™ 7 (E-Tile) | 1 | -1 | Not supported | 5 to 28.9 | data_rate/40 |
2 | -2 | Not supported | 5 to 28.3 | data_rate/40 | |
-3 | Not supported | 5 to 25.6 | data_rate/40 | ||
3 | -2 | Not supported | 5 to 17.4 | data_rate/40 | |
-3 | Not supported | 5 to 17.4 | data_rate/40 | ||
Agilex™ 5 E-Series (Device Group B) | -4 | Not supported | 17.16 | data_rate/40 | |
-5 | Not supported | 17.16 | data_rate/40 | ||
-6 | Not supported | 17.16 | data_rate/40 | ||
Agilex™ 5 E-Series (Device Group A) / D-Series | -1 | Not supported | 28.1 | data_rate/40 | |
-2 | Not supported | 28.1 | data_rate/40 | ||
-3 | Not supported | 28.1 | data_rate/40 | ||
Stratix® 10 (E-Tile) | 1 | -1 | Not supported | 5 to 28.9 | data_rate/40 |
-2 | Not supported | 5 to 25.6 | data_rate/40 | ||
2 | -1 | Not supported | 5 to 28.3 | data_rate/40 | |
-2 | Not supported | 5 to 25.6 | data_rate/40 | ||
3 | -1 | Not supported | 5 to 17.4 | data_rate/40 | |
-2 | Not supported | 5 to 17.4 | data_rate/40 | ||
-3 | Not supported | 5 to 17.4 | data_rate/40 |
*Maximum data rate may reduce with ECC enable. Please refer to Agilex™ 5 FPGAs and SoCs Device Data Sheet for more information.
1. Select Enable Soft PCS to achieve maximum data rate. For the TX IP core, enabling soft PCS incurs an additional 3–8% increase in resource utilization. For the RX IP core, enabling soft PCS incurs an additional 10–20% increase in resource utilization.
2. Refer to the Arria® 10 and Stratix® 10 Device Datasheet for the maximum data rate supported across transceiver speed grades and transceiver power supply operating conditions.
3. When using Soft PCS mode at 15.0 Gbps, the timing margin is very limited. You are advised to enable high fitter effort, register duplication, and register retiming to improve timing performance.
4. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is up to 12.288 Gbps.
5. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 11.0 Gbps.
6. For Arria® 10 GX 160, SX 160, GX 220 and SX 220 devices, the supported data rate is 10.0 Gbps.
2. Design Flow and IP Integration
IP Integration Information
Topic | Agilex™ 7 | Stratix® 10 | Arria® 10 |
---|---|---|---|
Synchronized | |||
Unsynchronized |
|
3. Board Design and Power Management
Topic | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Arria® 10 | Cyclone® 10 | Max® 10 |
---|---|---|---|---|---|---|---|
Pin Connection Guidelines | |||||||
Schematic Review Worksheets | |||||||
Board Design Guidelines | |||||||
Power Management | |||||||
Thermal Power Management | |||||||
Power Sequencing |
4. Interoperability and Standards Testing
Topic | Agilex™ 7 JESD204C |
Stratix® 10 JESD204B |
Stratix® 10 JESD204C |
Arria® 10 JESD204B |
---|---|---|---|---|
Interoperability Checkouts Reports | ||||
Hardware Checkouts Reports |
5. IP and Design Examples User Guides
Table 3: Consolidated JESD204B and JESD204C Resources
Topic | Agilex™ 7 JESD204B |
Agilex™ 7 JESD204C |
Agilex™ 5 JESD204B |
Agilex™ 5 JESD204C |
Agilex™ 3 JESD204B |
Stratix® 10 JESD204B |
Stratix® 10 JESD204C |
Cyclone® 10 JESD204B |
Arria® 10 JESD204B |
Stratix® V JESD204B |
Arria® V JESD204B |
Cyclone® V JESD204B |
---|---|---|---|---|---|---|---|---|---|---|---|---|
IP User Guide | ||||||||||||
Design Examples User Guide |
6. Training Courses and Videos
FPGA Technical Training
Video Title |
Description |
---|---|
This online course provides a broad overview of the JESD204B FPGA IP core. For better understanding of all the terms and concepts used in the course, we begin with a discussion of the relevant portions of the JESD204B interface specification, and followed by a presentation of some of the important features of the JESD204B FPGA IP core. Finally, a data flow of the system is used to describe the functional details of the core. |
FPGA Quick Videos
Video Title |
Description |
---|---|
Agilex™ 7 FPGA F-Tile JESD204C Demo Video | The JESD204B/C standards have been supported on several generations of FPGAs. Watch this demo on how JESD204C works on an Agilex™ 7 FPGA. |
Learn about the interoperability of JESD204B FPGA IP core on the Arria® 10 FPGA with the AD9144 converter from Analog Devices Inc. (ADI). |
|
How to interoperate ADI AD9680 with FPGA JESD204B IP Core on Stratix® V FPGA |
Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B FPGA IP core. |
How to interoperate ADI AD9680 with FPGA JESD204B IP on Stratix® V |
Get a step-by-step guide on how to set up the hardware, configure the analog-to-digital converter, and configure the JESD204B FPGA IP core. |
How to interoperate TI DAC37J84 with FPGA JESD204B MegaCore on Stratix® V FPGA |
Learn about the interoperability of JESD204B FPGA IP core on the Stratix® V FPGA with the DAC37J84 converter from Texas Instruments. |
Learn about JESD204B standard and the JESD204B FPGA IP solution. Find out how you can easily create a design example that works on hardware. |
|
Learn about the interoperability of JESD204B FPGA IP core on the Arria® V FPGA with the DAC37J84 converter from Texas Instruments. |
7. Debug
Tools
Document Title | Description |
---|---|
The objective of this debug FTA example is to help troubleshoot and identify issue related to Altera JESD204B IP Core and resolve it effectively. |
User Guides
Topic | Agilex™ 7 JESD204B |
Agilex™ 5 JESD204C |
Stratix® 10 JESD204B |
Arria® 10 JESD204B |
Cyclone® 10 GX JESD204B |
Stratix® V JESD204B |
Arria® V JESD204B |
Cyclone® V JESD204B |
---|---|---|---|---|---|---|---|---|
FPGA IP Overview | ||||||||
IP Core Debug Guidelines | ||||||||
Transceiver High-Speed Link Tuning Quick Guide | ||||||||
Ethernet Link Inspector |
Intellectual Property (IP) Core Release Notes
Topic | Agilex™ 7 JESD204B |
Agilex™ 7 JESD204C |
Agilex™ 5 JESD204B |
Agilex™ 5 JESD204C |
Agilex™ 3 JESD204B |
Stratix® 10 JESD204B |
Arria® 10 JESD204B |
Cyclone® 10 GX JESD204B |
Stratix® V JESD204B |
Arria® V JESD204B |
Cyclone® V JESD204B |
---|---|---|---|---|---|---|---|---|---|---|---|
FPGA IP | |||||||||||
E-Tile | |||||||||||
F-Tile | |||||||||||
GTS |
Additional Resources
Topic | Agilex™ 7 | Agilex™ 5 | Agilex™ 3 | Stratix® 10 | Cyclone® 10 | Cyclone® 10 GX | Arria® 10 |
---|---|---|---|---|---|---|---|
E-Tile Transceiver PHY | |||||||
F-Tile Architecture | |||||||
L-Tile and H-Tile Transceiver PHY | |||||||
PHY Lite for Parallel Interfaces | |||||||
PHY Transceiver |
For additional information, search the following resources: Documentation, Training Courses, Videos, Design Examples, and Knowledge Base.