AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
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Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

This high speed signal interface design guideline helps you design best-in-class board layouts for high speed signals operating up to 28 Gbps.

These guidelines are based on the latest results of 3D board layout simulations and measurement.There are test coupons to validate this guideline methodology and evaluate the recommended layout guideline properly. Intel recommends that you read this guideline thoroughly and perform pre-layout and post-layout 3D simulations to confirm that your channel meets specifications.

Note: The content in this application note is based on currently available simulations and measurement data. It is subject to change pending new data. In the future revisions we will also focus on other high speed interfaces and backplane board layout design guidelines.

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