AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Public
Document Table of Contents

Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

Document Version Changes
2019.03.12

Updated maximum transceiver data rates. NRZ was 30 Gbps, is 28.9 Gbps, PAM4 was 56 Gbps, is 57.8 Gbps.

2018.08.14 Global editorial changes only.
2017.05.08 Updated the capacitor from 0404 to 0402 in the "AC Coupling Capacitor Layout and Optimization Guidelines" topic.
2016.11.11 Initial release.

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