AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

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ID 683132
Date 3/12/2019
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Document Table of Contents
Document Table of Contents x
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline x
Intel® Stratix® 10 Devices and Transceiver Channels PCB Stackup Selection Guideline Recommendations for High Speed Signal PCB Routing FPGA Fan-out Region Design CFP2/CFP4 Connector Board Layout Design Guideline QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline SMA 2.4-mm Layout Design Guideline Tyco/Amphenol Interlaken Connector Design Guideline Electrical Specifications Document Revision History for AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline
FPGA Fan-out Region Design x
Signal Break-out Recommendations FPGA Fan-out Region Routing Recommendations AC Coupling Capacitor Layout and Optimization Guidelines
Signal Break-out Recommendations x
Option 1: Via-In-Pad Topology Option 2: Dog-bone with GND Cutout at BGA Pad Topology Option 3: Micro-via Topology GND Cutout Under BGA Pads in Fan-out Configuration Comparison of Dog-bone with GND Cutout Under the BGA and Via-in-Pad Configurations Trace Shape Routing at the BGA Void Area (Tear Drop Configuration)
FPGA Fan-out Region Routing Recommendations x
Comparison of Conventional and Recommended Break-out Routing Topologies
Comparison of Conventional and Recommended Break-out Routing Topologies x
Conventional Jog-out Routings with Skew-matching Right After Break-out The Impact of Via Height and Via Anti-pad Over Insertion Loss
AC Coupling Capacitor Layout and Optimization Guidelines x
0201 AC Capacitor 0402 AC Capacitor PCB AC Capacitor Placement Layout Recommendation
0201 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width only on the First GND Plane Under the Capacitor
0402 AC Capacitor x
Sweeping Anti-pad Radius Sweeping Void Width Only on the First GND Plane under the Capacitor Adding a Trace Reference to the 0201 AC Capacitor Adding a Trace Reference to the 0402 AC Capacitor
PCB AC Capacitor Placement Layout Recommendation x
What to Avoid for AC Capacitor Configuration
CFP2/CFP4 Connector Board Layout Design Guideline x
CFP2 Host Connector, Module Assembly, and Pinout CFP4 Host Connector, Module Assembly, and Pinout Recommended PCB Design Guideline at the CFP2/CFP4 Connector CFP4 Design Example and Optimization Performance
CFP4 Design Example and Optimization Performance x
CFP4 Connector Layout: Signal Via, Trace Routing Impact, and Optimization Two Different Break-out Routings at the CFP4 Connector Area CFP4 Connector Routing Topologies Design Example Full CFP4 Channel Analysis Design Example (Excluding the Connector) CFP2 Connector Area Layout
QSFP+/zSFP/QSFP28 Connector Board Layout Design Guideline x
QSFP+ Module Assembly and Pinout Recommended PCB Design Guideline for QSFP+/zQSFP/QSFP28 Channels Recommended QSFP+ Signal Routing QSFP28 Example Design and Performance Optimization
SMA 2.4-mm Layout Design Guideline x
SMA 2.4 mm Molex® Connector Assembly PCB Design Guidelines for Channels Using the 2.4 mm Connector 2.4 mm Example Design Performance
PCB Design Guidelines for Channels Using the 2.4 mm Connector x
Recommended PCB layout Design for Version-A SMA 2.4 mm Connector Recommended PCB layout Design for Version-B SMA 2.4 mm Connector Performance Comparison between Option1 and Option2 layout Other 2.4 mm Connectors 2.4 mm Channel Specifications
Tyco/Amphenol Interlaken Connector Design Guideline x
Connector Signal and Pin Assignment
Connector Signal and Pin Assignment x
PCB Design Guidelines for Channels with 25 Gbps + Interlaken Interface Connector Recommendations Interlaken Channel Interface Performance Example
Electrical Specifications x
CEI 28 Very Short Reach (VSR) Specifications for CFP2/CFP4/QSFP+/QSFP28/zQSFP/SMA 2.4 mm Interlaken Interface Specification
Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

QSFP28 Example Design and Performance Optimization

This section describes the optimization performed at the connector for the best insertion and return loss and crosstalk (isolation) performances of the channel.

Figure 79. QSFP28 Layout Design at the Connector with One Layer GND Cutout Below the Connector Pads (W(mil) x L(mil))The performance results here are achieved by using a GND cutout at 50 mil x 65 mil, 67 mil x 75 mil, and the recommended 100 mil x 110 mil.

In the figure above, the signal finished drill size is 8 mil, the via pad is 18 mil, and the rectangular differential via-anti-pad is 45 mil x 80 mil. The signal via to signal via pitch in one pair is 40 mil. The signal via to GND via pitch is 27 mil. Routing is on layer 5. All signal vias are back-drilled up to layer 6.

The reference design is considered without the GND cutout below the connector pads (blue reference design in Figure 80). The performance in Figure 79 is observed by using various GND cutout (W) mil x (L) mil below each transceiver pair. W is swept from 50 mil to 100 mil and L from 65 mil to 110 mil. The GND cutout had been applied only on GND layer#2 as shown in Figure 79

In the figure above, the differential return loss performance is from the stripline trace ports.

Figure 80. Differential Insertion Loss PerformanceThe blue reference design has no GND cutout.

The green design features a GND cutout at 50 mil x 65 mil.

The brown design features a GND cutout at 67 mil x 75 mil.

Intel recommends the red design which features a GND cutout at 100 mil x 110 mil.

Figure 81. Differential Return Loss PerformanceThe blue reference design has no GND cutout.

The green design features a GND cutout at 50 mil x 65 mil.

The brown design features a GND cutout at 67 mil x 75 mil.

The red design features a GND cutout at 100 mil x 110 mil.

Intel recommends the red design which features a GND cutout at 100 mil x 110 mil.

The figures above indicate that the recommended GND cutout has the best performance compared to all the others.

To further optimize the layout structure in Figure 79, two GND reference diving boards for stripline trace routing have been added.

Figure 82. QSFP28 Layout Design at the Connector with Added GND/Reference Diving BoardsReference diving board structures are on layers 4 and 6. The diving board width is twice the width of the outer edge-to-edge of the differential lanes. The length of the diving board is extended up towards the signal via.
Figure 83. Differential Insertion Loss PerformanceGND cutout below the connector is fixed at 67 mil x 75 mil.
Figure 84. Return Loss PerformanceGND cutout below the connector is fixed at 67 mil x 75 mil.

The addition of reference diving boards enhances both insertion and return loss performance.

To improve isolation between the two pairs, you can insert an additional GND via between the signal pairs. Most of the crosstalk will occur through vertical coupling between signal vias of two different signal pairs. Therefore, adding one GND via will enhance the isolation.

Figure 85. QSFP28 Layout Design with Added GND Vias
Figure 86. FEXT and NEXT Crosstalk PerformanceGND cutout below the connector is fixed at 67 mil x 75 mil.
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