AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Document Table of Contents

PCB Design Guidelines for Channels Using the 2.4 mm Connector

Observe the following guidelines when designing for channels using the 2.4 mm connector:

  • Refer to PCB Stackup Selection Guideline chapter for the selection of stackup and routing layers.
  • Intel recommends a routing trace impedance of 95Ω loosely differential, or 47.5 Ω single-ended. Refer to FPGA Fan-out Region chapter for break-out routing at the FPGA.
  • Use the minimum routing length possible to minimize insertion loss and crosstalk.
  • Refer to the AC coupling layout design guide in AC Coupling Capacitor Layout and Optimization Guidelines chapter, because all RX paths require AC capacitors.
  • Match the length (less than 2 ps) for all TX and RX paths if required. Refer to Recommendations for High Speed Signal PCB Routing chapter for the length matching strategies at the FPGA.
  • Use a back-drill for all transceiver signal vias.
  • The Molex connector and cutout are standard recommendations made by Molex. This is a surface-mounted connector, and there is always a back-drill for the signal vias for transferring signals from the top layer to the inner layers.

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