AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Document Table of Contents
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Recommendations for High Speed Signal PCB Routing

To achieve better performance for high speed channels, follow these guidelines:

  • TX and RX signal routing must be isolated using separate stripline layers for critical high speed interfaces above 15 Gbps.
  • Intel recommends that the RX signal routing layer be located above the respective TX signal routing layer. This means that the RX routing layer must be separated from TX routing layer. When FPGA's are located on top layer and all high speed vias are back drilled from bottom, Intel recommends RX layers on upper layers and TX layers on those layers below RX layers. The scenario will be opposite if FPGA's are located on bottom layer. In that case, RX layers are recommended on bottom layers and TX layers are recommended on those layers above RX layers.
    • RX signals are always weaker than TX signals. Obtaining shorter transition via length for RX signals reduces mismatching and reflection, and more RX signal power is received at the device.
    • Most of High Speed Interfaces require AC coupling caps on RX signal lanes. Intel recommends RX routing on upper layers close enough to top layer. By this, designer can achieve shorter signal via transition height and eventually reduce reflection on RX path.
    • AC caps can also be mounted on the bottom layer of the PCB. Intel recommends this for signal data rates below 15 Gbps. In this case, you can select the RX signal routing layer as a stripline as close as to bottom layer as possible.
  • Ensure that you have a good contiguous and un-interupted ground reference plane for high speed signal routing.
    • Avoid using the power plane as reference plane for critical high speed signal routing above 15 Gbps.
    • Void regions along, underneath and above the high speed signal routing is prohibited.
    • Always maintain enough space from the edge of the signal trace to the edge of the void region to avoid mismatching due to lack of sufficient reference plane. Spacing should at least be the signal trace width. Intel recommends to have this space be equal or larger than trace width in break-out region.
    • To avoid cross talk between adjacent pairs, make sure to have enough space between pairs routed on the same layer. The rule is to keep at least 3x (the height of signal to reference plane or the width of signal trace, whichever is larger) for the space between adjacent pairs.
  • You must back drill for all high speed signal transition vias.
    • Back drill can be applied from either top or bottom layer, depending on the FPGA and the connectors that have been mounted on top or bottom layers. This emphasizes which part of via as extra stub is needed to be removed.
  • Remove all non-functional via pads for both signal and GND return path vias.