AN 766: Intel® Stratix® 10 Devices, High Speed Signal Interface Layout Design Guideline

ID 683132
Date 3/12/2019
Public
Document Table of Contents

2.4 mm Example Design Performance

The layout design strategy in the previous section showed the implementation at the connector area.

Figure 95. Arria10 device SI Development Kit Channel Layout for the TX0 LaneThe total trace length is approximately 4.5 inch excluding the connector.
Figure 96. Magnified Single-ended TDR measurement from the ConnectorThe TDR rise time used for below measurement < 17 ps.

The signal via impedance reaches 45 Ω at the minimum and to 55 Ω by transition from signal via to the main inner layer routing.

Figure 97. Single-ended Scatter Parameters S21 and S22 (from the Connector)

The single-ended insertion loss is approximately 5 dB and the return loss is approximately -12 dB at 14 GHz.

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